Cheri-research/Toooba
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4131dcd0734bdf036a98e1c689b3d0912d2f3cd8
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244 Commits

Author SHA1 Message Date
jon
fa9931b64c Implement a couple Cache counters in the LLCache. 
These aren't too useful... We don't seem to have normal counters for
loads and stores in the baseline.
 2020-12-15 18:16:21 +00:00
jon
17a7a32092 Use DRegOR instead of immitating latching behaviour. 2020-12-15 16:18:36 +00:00
jon
b6a397df52 Support for ICache stat counters. 2020-12-15 14:49:16 +00:00
jon
73d25bf8f5 Support performance counters (hopefully) in the caches. The DCache 
should be fully wired up.
 2020-12-14 18:10:06 +00:00
Jessica Clarke
f6569e2d14 Actually do the intended fix, not just inverting the variable 2020-12-14 10:51:57 +00:00
Jessica Clarke
295b878836 Fix negated CYCLE/INSTRET logic for ASR and make less confusing 2020-12-14 10:50:23 +00:00
jon
6768bf92c7 iMove the store count to the pipeline write. 
It appeared to be counting capabilities in store counter flushes, which,
FI think, is not quite what was intended in this counter.
 2020-12-11 17:16:38 +00:00
jon
19a07882ab CSome style cleanups from chat with Alexandre. 2020-12-11 16:44:59 +00:00
jon
1bae03da9c Implement all the remaining core (not cache) memory stat counters. 2020-12-11 15:48:10 +00:00
jon
d6243be1dd Add a few more core performance counters. 2020-12-04 18:34:56 +00:00
jon
f42c3f3577 Merge branch 'cheri-perfmon' into CHERI 2020-12-04 16:29:51 +00:00
jon
5665d2e9cd A more effective Fence count (as some fences go through as the Nop 
iType).
 2020-12-04 16:28:19 +00:00
jon
1fb388fb18 Count more things correctly. 2020-12-03 17:54:46 +00:00
jon
4fcc18635a Supporting most architectural counters, wiring them out from 
CommitStage.
Also support multiple events per cycle.
 2020-12-02 15:28:41 +00:00
jon
e99e1e6274 Update CSR names to fullish standard names. 2020-12-02 10:18:25 +00:00
jon
259d34618c A design that actually passes one performance monitor trace from 
TestRig.  The example counted redirections, which happend to match
between Flute and Toooba for this example.
 2020-12-01 18:02:11 +00:00
Alexandre Joannou
98a9c076cd Update BlueStuff API and Bump BlueStuff and TagController 2020-12-01 14:22:12 +00:00
Jonathan Woodruff
0289bfe17d Fix a couple errors due to changes somehow merged over from the rich_predicted_state branch. 2020-11-09 11:14:11 +00:00
Jonathan Woodruff
69c697daf7 Changes needed to build for FPGA. 2020-11-06 11:44:33 +00:00
Nathaniel Filardo
d4308f0f03 Slightly rework CHERI PTE to add CapDirty flag 
Permissions are consistently checked before dirty flags, now, too.
 2020-09-30 15:40:50 +01:00
jon
00ffdd7228 Enable to build with latest BSC compiler. 2020-08-11 14:46:28 +01:00
jon
8896bb27f1 Revert "Remove the special flush from the Fetch3 stage." 
This reverts commit 4fe24c9cd5.
 2020-07-29 11:40:00 +01:00
jon
4fe24c9cd5 Remove the special flush from the Fetch3 stage. 
This is an intermediate simplification for moving to SupFifo-based picking.
 2020-07-29 07:40:15 +01:00
Peter Rugg
3132f9f55f Trap when writing PCC, rather than silently ignoring 2020-07-28 12:57:13 +01:00
Jessica Clarke
73dedec309 FetchStage: Use map rather than for loop 
Also add some spaces in the following line.
 2020-07-24 20:02:10 +01:00
jon
40af067a71 Fix RVFI_DII build in the presence of 2-byte bundles. 2020-07-24 17:30:29 +01:00
jon
1f968b0c07 2-byte aligned instruction memory to simplify compressed instruction 
fetch.
 2020-07-24 12:38:37 +01:00
Peter Rugg
ecce475b97 Merge branch 'mem_perm_checks' into CHERI 2020-07-23 16:53:14 +01:00
Peter Rugg
27082ee2a9 Report writes to PCC as illegal instruction, not ASR violation 2020-07-23 15:40:28 +01:00
Peter Rugg
e8aa873c2e Prevent 'insufficient type info' warning 2020-07-23 11:18:31 +01:00
Peter Rugg
a6b40e946b Prevent using CCSeal to 'seal over' other types 2020-07-23 11:18:07 +01:00
Peter Rugg
c693462f6b Add tag-clearing due to cap load perm and PTE bits 2020-07-22 15:54:49 +01:00
Peter Rugg
0040b05ada Add page table cap store checking 2020-07-21 16:02:37 +01:00
Jessica Clarke
2f4f5ca838 FetchStage: Reduce diff to upstream 2020-07-21 14:36:36 +01:00
Jessica Clarke
0516db5e8d Bump BSV-RVFI-DII and refactor to support new parcel-based interface 
This means FetchStage should now behave in the same way with RVFI-DII as
with an I-Cache. A Dii_Parcel_Id is fed alongside PC everywhere relevant
and follows very similar logic, but, importantly it's just extra state
on the side, it doesn't affect what we do with the branch predictor and
parcel combining/instruction decoding logic.
 2020-07-21 14:36:36 +01:00
jon
7d98946103 Working compressed instruction support. 2020-07-20 19:49:52 +01:00
jon
d7a4d3497b Keep unaligned instruction fetch from breaking DII. 2020-07-17 16:39:13 +01:00
jon
4d2f971767 Assign the correct PC to fetched instructions. 2020-07-17 11:07:19 +01:00
Jessica Clarke
2b8e5f1dad FetchStage: Inline unnecessary local variable 2020-07-16 18:13:43 +01:00
Peter Rugg
a74596c956 Fix CCall being impossible 
The cap to be checked (rs1) was being overwritten with the unsealed jump
target before the type was checked
 2020-07-16 14:06:26 +01:00
Jessica Clarke
5efd7d5cd8 Partially bring back tval 
We need this to determine which 16b parcel of a 32b instruction caused
the fault (omitting this caused rv64uc-v-rvc to fail).
 2020-07-15 04:27:25 +01:00
Jessica Clarke
7eff218288 Replace enums-for-constants with structs wrapping a plain Bit#(n) 
BSC does not play nicely with enums whose labels do not start at 0 and
increase linearly. Instead, in such cases, it generates a whole bunch of
conditions to "legalise" any read values, which causes an explosion of
logic in places like the ROB. Thus, use this ugly (but still typed)
alternative that, other than naming conventions enforced by BSC, looks
almost the same as an enum.
 2020-07-15 03:16:24 +01:00
Peter Rugg
b44a912756 Don't require ASR to read PCC 
The dInst.scr field was accidentally left populated in this case,
causing the check to occur
 2020-07-14 22:41:51 +01:00
Jessica Clarke
6356d5f8a1 Drop check against whether the ROB row already has a trap 
The only other thing setting this is enq, but RenameStage marks
already-trapping instuctions as Executed so they should never go to the
ALU.
 2020-07-14 16:46:29 +01:00
Jessica Clarke
f2d9c78824 Drop unused exception parameter on FPU ROB ports 
This gives traceBundle its own set of ports. Also fix the nonsensical
calculations for those Ehr ports; the number of FPUs should not be
calculated as ALUs/2!
 2020-07-14 16:37:59 +01:00
Jessica Clarke
0b7d635cbf Drop unused store_data/store_data_BE arguments when TV is disabled 2020-07-14 16:23:10 +01:00
Jessica Clarke
5a42b0102a Turn pc back into a Reg 
This is from before we fed bounds all the way back to the BTB and RAS.
We no longer need this and can go back to what upstream does.
 2020-07-14 16:22:52 +01:00
Jessica Clarke
9bdf71ee4e Only store the actual address for completed loads/stores 
This is only needed for RVFI tracing and for xtval if we trap, so we
never need the full capability.
 2020-07-14 16:22:50 +01:00
Peter Rugg
675caad0ac Trap for permission failures on mem access 2020-07-14 15:34:38 +01:00
Jessica Clarke
26a5376f9c FetchStage: Tidy up comment that no longer applies 
Block is now entirely for debugging only.
 2020-07-13 18:23:01 +01:00