Made the proc start method non-blocking on mmio platform and wired in a new way
to set the tohost addr using a control and status request, and bumpped
WindCoreInterface accordingly
This means FetchStage should now behave in the same way with RVFI-DII as
with an I-Cache. A Dii_Parcel_Id is fed alongside PC everywhere relevant
and follows very similar logic, but, importantly it's just extra state
on the side, it doesn't affect what we do with the branch predictor and
parcel combining/instruction decoding logic.
testing.
To make this not fail, remove the reset server behaviour in SoC_Top
which appears to not be needed as it is only calling reset servers upon
actual reset when everything has been reset anyway.
I suppose these reset servers are meant for debug-unit-initiated reset
events.
I couldn't quite use the implementation from Flute as the register was
too wide for verilator.
This one uses wide memories instead, which is way complicated, but I
think it works. The width of the memory can be traded off for reset
speed. The width at the moment is 8192 bits, which seems to be fast
enough.
Now able to run multiple ISA tests in a single simulation run
connected to remote debugger DSharp, using either hart_reset or
ndm_reset between tests to bring the system back into reset state.
All Debug Module commands working:
- dm_reset, hart_reset, ndm_reset
- break (set breakpoint)
- step
- continue (until breakpoint of 'halt' command)
- halt
- read/write GPR, FPR, CSR, memory
- elf_load
After a test, GDB can write DCSR to restore to Machine privilege,
write to PC (DPC) to restore boot value,
write MSTATUS to restore to initial value,
then can load and run next test.
Detail: an "instruction-fetch" response from mmioplatform to core
should be an "InstFetch". This was true for successful fabric reads,
but on error responses it was wrongly returned as a "DataAccess"
response. This was causing a deadlock.
Regression status: RV64ADFIMSU_Toooba_verilator 204/229 PASS
(22 expected floating-point failures due to inaccurate modeling)
Modified
src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv
Renamed 'BootRom' to 'IODevice'
Imported and instantiated SoC_Map
changed method getFetchTarget to use soc_map.is_IO_addr (phyPC)
to classify as IODevice
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
Changed 'BootRom' constant to 'IODevice' constant (just a renaming)
src_Testbench/SoC/SoC_Map.bsv
Changed boot rom classification from 'mem' to 'IO device'
New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14]. The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either. Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.
Builds in standalone mode, runs ISA tests.
Builds in src_SSITH_P3, generating RTL.
