Cheri-research/Toooba
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103835db72ba356feaa1dc21ca5e795b58ffec00
Commit Graph

367 Commits

Author SHA1 Message Date
Peter Rugg
b232272ad1 Treat CCSeal with an out-of-bounds capability as a move 
See 2d7ae22c0a for corresponding Sail change

This is not the nicest approach for area, but integrating with the existing bounds check would delay the result a cycle, and incur additional complexity.
 2021-04-08 13:08:46 +01:00
jon
12ac14c1ca Move to config registers here as this affects scheduling. 2021-04-07 17:47:49 +01:00
Franz Fuchs
ad044689cb added some of the performance counters in the L2 TLB 
- count L2 TLB accesses
- count L2 TLB misses
- count L2 TLB flushes
 2021-04-01 16:18:18 +01:00
Franz Fuchs
6e157fff5a Small improvement of BTB changes made by Jon and myself 2021-04-01 09:08:47 +01:00
jon
c17eb9e7c1 Finish propagating BTB name change from previous commit. 2021-04-01 09:04:31 +01:00
jon
0701dea9a9 Preserve name for verilog so component.xml doesn't have to be fixed. 2021-04-01 07:08:46 +01:00
Franz Fuchs
4b531fac46 Made the hash size in the BTB configurable 
The current configuration is a tag of 16 bits width
 2021-03-31 17:46:27 +01:00
jon
84271b2712 Changes to build (and run?) with TSO_MM. 2021-03-29 12:03:27 +01:00
jon
5e687a972a Slight cleanups from review with Alexandre. 2021-03-24 12:21:00 +00:00
jon
07dd70d77b Associative 2-way associative BTB. 
Also, 16-bit hashed tags.  (This is because the only full-speed
implementation required duplicating the tags).
This implementation uses the MAP library, and a new BRAM instance of it.
 2021-03-24 09:56:25 +00:00
jon
20e2249761 Make map associative in preparation for associative BTB. 
Also make jump alias predictor smaller and associative.  (2x64 entries
instead of 256 entries)
 2021-03-23 11:26:43 +00:00
Jonathan Woodruff
2bfe25dfad Update Map.bsv 
Remove unused function.
 2021-03-22 20:28:34 +00:00
jon
d351eeee11 Increase BTB to 1024 entries. 
(On FPGA we can make this as large as we like, but returns diminish.
This one has a chance of being reasonable for ASIC I guess?)
 2021-03-22 18:20:22 +00:00
jon
30bd5e7f46 Allow entries in the load kill predictor to be "False" so that they can 
be invalidated.
Also invalidate entries "randomly" to prevent a steady-state of waiting
for all stores to complete on 1/256 loads even when no aliasing is going
on.

Remove debugging prints.
 2021-03-22 18:14:33 +00:00
jon
791927f852 Prediction for whether a load will have an aliasing store. 2021-03-22 18:14:33 +00:00
jon
8de3cfffeb Remove debug print statements. 2021-03-10 17:03:35 +00:00
Jonathan Woodruff
6ef565e56c Fix bugs in previous commit due to test build not using performance 
counters.
 2021-03-09 16:05:01 +00:00
jon
1ef2d0cbeb Include both execute redirect and commit redirect in "redirect" counter. 2021-03-09 15:57:15 +00:00
jon
fe7977e4e9 Fix typo when removing commented out code. 2021-03-06 07:24:49 +00:00
jon
8da520175f Use an (unguarded) BRAM in the Btb. 
Also, assume that a target that is not taken should be removed from the
Btb.  (The read that checked isn't possible with BRAM timing unless we
latched and had an extra port, but removing the check actually improved
performance a bit in CoreMark, and the pipeline should actually only be
reporting a non-taken branch if we did something wrong.)
 2021-03-06 07:19:50 +00:00
jon
4b411bf752 A Btb with 1/4 the storage that will (hopefully) infer as BRAM. 2021-03-05 12:14:26 +00:00
jon
7aea0325fc Add cycles to commit instruction reports to help with performance 
debugging.
 2021-03-05 12:12:33 +00:00
jon
89f0c3a45f Reduce verbosity. 2021-03-05 12:11:49 +00:00
jon
6ea387f744 Fix performance bug in PC compression where we execute across a page 
boundary.
 2021-03-04 14:41:50 +00:00
Peter Rugg
7a1d234e40 Merge branch 'ifetch-cleanup' into CHERI 2021-03-02 11:57:31 +00:00
Jessica Clarke
e1060ac43d TlbTypes: Fix exception code reported for some store page fault conditions 
The mode and well-formedness checks above also set fault to True, so we
end up with cases where a DataStore request uses the default load page
fault exception code. Instead, unconditionally set excStorePageFault for
DataStore, and conditionally override to excStoreCapPageFault when
appropriate, being particularly careful to ensure earlier exception
causes still take precedence.

Also restructure the InstFetch and DataLoad cases to match how DataStore
needs to look.

This fixes the rv64si-p-dirty ISA test, currently the sole failure.
 2021-02-28 03:51:05 +00:00
Jessica Clarke
c7bd60b47e CSRs: Don't guard HPM CSRs with PERFORMANCE_MONITORING 
They always exist, just WARL so can be hard-wired.
 2021-02-28 01:11:39 +00:00
jon
9d5095b076 Count CJALRs with Jrs. 2021-02-24 20:36:46 +00:00
Jessica Clarke
df430e22c8 Exec: Enable non-ASR access to TIME 
This is needed for benchmarking.
 2021-02-24 04:17:42 +00:00
Jessica Clarke
7776bac8b5 Exec: Enable non-ASR access to HPMCOUNTERn 
These are now defined, and needed for benchmarking.
 2021-02-23 20:35:18 +00:00
Peter Rugg
5b6e8d88f6 Add CSetEqualExact 2021-02-22 17:44:36 +00:00
jon
2f0b0c110f Use the necessary number of ports. 2021-02-19 17:38:16 +00:00
jon
b5bce1209a Revert "Revert biggest scheduling change from potentially problematic commit." 
This one does not actually build with the new BSC compiler.  I forgot to
test the hardware build (with GDB), which is where we have the problem.
This reverts commit b4308e9a6e.
 2021-02-19 17:38:16 +00:00
Peter Rugg
9f0968b1cb Fix AXI_Size=16 for MMIO of caps 2021-02-19 17:19:47 +00:00
jon
b4308e9a6e Revert biggest scheduling change from potentially problematic commit. 
This still builds with the new BSC compile.
 2021-02-18 15:18:58 +00:00
jon
0f3fd15d41 Initial implementation of map of HPM counters into supervisor and user 
mode.  This version just unconditionally exposes them.
 2021-02-17 17:07:53 +00:00
Alexandre Joannou
4c19a34eda Workaround for scheduling issues when using PERFORMANCE_MONITORING (with jdw57) 2021-02-15 18:07:08 +00:00
jon
9e36ff95cd Roll back accidental commit of experimental change. 2021-02-11 12:22:00 +00:00
jon
40ea082310 Some updates to build with the new bsc compiler. 2021-02-10 17:22:26 +00:00
Peter Rugg
a78d09c522 Add ifdefs for GDB control on helper functions 2021-02-08 14:49:13 +00:00
Jessica Clarke
fb5339e9ca Adapt the PLIC instantiation and wiring to support multiple cores 2021-01-31 17:54:43 +00:00
Peter Rugg
cedb4c279d Ensure the MMIO platform issues aligned requests by changing the AXI4_Size field based on the byte enables 2021-01-31 17:34:35 +00:00
Peter Rugg
44e19afbf3 Fix MMIO bug missing uncached instruction bytes with certain alignments 2021-01-30 15:22:22 +00:00
Peter Rugg
d340066f6f Multicore debug cleanups 2021-01-21 20:51:02 +00:00
Peter Rugg
30e7090213 Multicore debug-module 2021-01-21 20:30:07 +00:00
Peter Rugg
3417fb454e Revert "Provide opt-in wedge debugging info" - some missed changes 
This reverts commit 68d3bd484e.
 2021-01-21 20:30:07 +00:00
Peter Rugg
e8487e2a1c Revert "Provide opt-in wedge debugging info" 
This reverts commit 68d3bd484e.
 2021-01-19 22:00:16 +00:00
Peter Rugg
20f1ddf587 Revert "Plumb through a lot more ROB debug state" 
This reverts commit 0f65994955.
 2021-01-19 21:40:59 +00:00
Peter Rugg
a6ab823d1d Revert "Cover interesting fetch and rename state for DEBUG_WEDGE configs" 
This reverts commit 5e9b478371.
 2021-01-19 21:39:59 +00:00
jon
c515fb4518 Remove commented-out code. 
Enable building with open-source BSC.

Resolve a couple issues brought up by Jess.

Remove a stray space (as noted by Jess).
 2021-01-14 17:10:04 +00:00