Cheri-research/Toooba
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37f6dbde93dddde9f701ebc4e231169a79aadde3
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480 Commits

Author SHA1 Message Date
Jonathan Woodruff
37f6dbde93 Timing optimisation for Tournament Predictor. 
Start global-history-indexed lookups in the previous cycle.
This is a general timing optimisation that should be pushed upstream at
some point.
 2022-01-12 16:08:33 +00:00
Jonathan Woodruff
1d6633f423 Buffer redirection from Commit to reduce conflicts in the pipeline. 
This is a general improvement, and should be upstreamed to master if
there are no issues discovered.
 2022-01-10 17:18:01 +00:00
Jonathan Woodruff
e600fd7d38 Delay BTB update by a cycle for timing. 
This should not be a primary degredation of performance since the
redirection gets on seperately from this update which will only affect
future predictions.
 2022-01-08 10:16:50 +00:00
Jonathan Woodruff
b84562a027 Improve scheduling for LatencyTimer to improve timing path discovered on 
DE10.
 2022-01-07 09:52:43 +00:00
Jonathan Woodruff
f619f4b0a1 Make the associative BTB compressed. 
That is, only store the bottom 16 bits of the target if the upper bits
of pc and nextPc match.
Have a single "way" dedicated to full targets.
 2021-12-20 17:24:55 +00:00
Jonathan Woodruff
34c6ee1894 Specifically give priority to wrong_spec when they conflict. 
This appears to yield 10% performance improvement as our default setup
appears to choose a wrong priority.
 2021-12-03 12:36:40 +00:00
Franz Fuchs
37074525e1 removed unnecessary execute permissions for Decode.bsv, Exec.bsv, ProcTypes.bsv, ReorderBuffer.bsv, and AluExePipeline.bsv 2021-11-29 10:38:23 +00:00
Jonathan Woodruff
59836cc9e5 Hopefully optimise this function to have just one call to modifyOffset. 2021-11-26 11:07:12 +00:00
Marno
0f86f09b6a Updated copyright statement 2021-11-11 12:15:45 +00:00
Marno
6ae92f786b Checking tag and seal on rVal2 and checking type on rVal1 in a way that does not use undefined behavior. 2021-11-11 11:36:45 +00:00
Marno
4d1dc29f79 Added ccopytype_bypass 2021-11-10 11:53:26 +00:00
Jonathan Woodruff
d5e52a9ecb Revert to upstream direction predictors to reduce diffs and prepare for 
improvements that can be upstreamed.
Basically, only use addresses in these predictors rather than
capabilities, and just pass an address in from the FetchStage.
 2021-11-05 17:42:19 +00:00
Franz Fuchs
001c5e8347 put changing the interrupt counter and writing back to a register in the right order 2021-11-05 13:47:39 +00:00
Jonathan Woodruff
836ed5b143 Merge branch 'jdw57-jr-bsc-safety' into CHERI 2021-11-03 16:46:21 +00:00
Jonathan Woodruff
cb1858447b Fix tracing of Sc. 
Sc is unique in that it writes both memory and a register value.
This implementation works around the fact that the memory store data and
the register write data are sharing the same field in the reorder buffer
by inferring the writeback value of Sc from the byteEnable field.
 2021-11-03 12:45:15 +00:00
Jonathan Woodruff
3908c5f955 A merge resolution not included in previous commit due to not saving file. 
Doh.
 2021-11-02 18:12:05 +00:00
Jonathan Woodruff
7437c0c5e7 Some cleanups. 2021-11-02 18:09:06 +00:00
Franz Fuchs
56173bf2c2 Added interrupt counter 2021-11-02 15:48:02 +00:00
Jessica Clarke
fb1a629e07 Decode: Fix capability width mode-dependent LR/SC 
All of St, Amo, Lr and Sc use the normal 3-bit encoding for the width;
rather than add Lr and Sc to the list, switch it just to exclude Ld as
the special case that's handled by the other half of the expression.

Previously LR.C and SC.C were decoded as LR.BU and SC.BU.
 2021-10-27 15:44:23 +01:00
Jonathan Woodruff
87785eb25c Don't translate invalid vaddrs in the DTLB. 2021-10-14 17:13:18 +00:00
Jonathan Woodruff
dad3d504b1 Take into account BTB predictions. 
nextPc only reflected things known in the Decode stage, but not before
(i.e. BTB predictions).
This meant that we were pretty much always redirecting JRs.
I needed to pipe through whether a jump was predicted by the BTB or not,
and then only stop predicting if there is no nextPc prediction and also
no BTB prediction.  This should actually reasonably approximate SBC.
Also, this one is not "redirecting", it's just flushing (flipping
decode_epoch_local), trusting that we'll get a later redirection.
 2021-10-11 16:23:45 +00:00
Jonathan Woodruff
3636f6239a Use Matt's slightly cleaner version of the function. 2021-10-11 16:23:22 +00:00
Jonathan Woodruff
1b5a036c46 Two fixes: do a proper "all bits are the same" function, as well as 
prepare a capability target to pass back.
 2021-10-08 16:35:42 +00:00
Jonathan Woodruff
5d5bee3e08 Use an invalid virtual address when preventing prediction, and also 
detect invalid virtual addresses in the TLB and miss rather than proceed
with page walking.
 2021-10-08 11:00:11 +00:00
Jonathan Woodruff
cec55419f5 Merge branch 'CHERI' into jdw57-jr-bsc-safety 2021-10-08 09:50:45 +00:00
Jonathan Woodruff
3d0aee0af4 Remove some verbosity from the committed state. 2021-10-07 16:30:32 +00:00
Jonathan Woodruff
81a12b89cb Move to NonPipelinedSquareRooter to hopefully fit more 
deterministically.
We're still waiting for a fixed NonPipelinedDivider.
 2021-10-07 16:28:57 +00:00
Jonathan Woodruff
520b09a6ed Use less wierd default value. 2021-10-07 16:17:19 +00:00
Jonathan Woodruff
fe9e000f43 Merge branch 'CHERI' into jdw57-jr-bsc-safety 2021-10-04 08:37:56 +00:00
Franz Fuchs
db54d27368 Move import DReg::* into ifdefs 2021-10-01 16:54:17 +01:00
Jonathan Woodruff
c69acc2fc4 Don't predict next instruction for JR without a BTB prediction. 2021-09-30 12:20:40 +00:00
gameboo
9657339d87 "fix" non PERFORMANCE_MONITORING build 2021-09-29 18:09:06 +01:00
Franz Fuchs
87977461a6 Merge branch 'CHERI' of github.com:CTSRD-CHERI/Toooba into CHERI 2021-09-29 14:23:20 +01:00
Franz Fuchs
cf8bfdc4a8 Merge branch 'faf28_hpm_consistency' into CHERI 2021-09-29 14:04:08 +01:00
Franz Fuchs
db9b5c7f54 re-integrated TagController 2021-09-24 11:39:23 +01:00
Peter Rugg
8ef44b0a6c Workaround single step wedges by not waiting for flush before halting 2021-09-24 10:33:58 +00:00
Franz Fuchs
4cfac08bca Bumped BlueStuff and made necessary adaptations 2021-09-23 15:25:46 +01:00
Franz Fuchs
9ea66bed86 Merge pull request #18 from CTSRD-CHERI/faf28_hpm_consistency 
Using HPM information from one central struct
 2021-09-20 13:21:52 +01:00
Franz Fuchs
9320e53720 Bumped RISCV_HPM_Events made minor changes 2021-09-17 10:38:48 +01:00
Jonathan Woodruff
c489a177d4 Fix type error. 2021-09-08 10:23:29 -05:00
Jonathan Woodruff
08231b7e5c Hopefully don't wedge on ifetch bus error. 
We think that we were wedging on IFetch bus error.
It appears that we didn't make the last instruction fragment valid in the bus error case, and expect that this path was not previously exercised.
This change returns 0s (to hopefully make the error less subtle) in exactly the right number of fragments.
 2021-09-08 10:11:25 -05:00
Franz Fuchs
b25d70a8cc performed corrections for CONTRACTS_VERIFY 2021-09-07 08:15:03 +01:00
Franz Fuchs
bc7eed67ab Did more cleaning up 2021-09-06 15:55:28 +01:00
Franz Fuchs
4c9d89e936 Performed a bit of cleaning up 2021-09-06 13:33:13 +01:00
Franz Fuchs
e33b4021d8 Integrated generateHPMVector function 2021-09-03 17:37:43 +01:00
Franz Fuchs
61d788ebc7 define No_Of_Evts in StatCounters 2021-09-03 14:14:32 +01:00
Franz Fuchs
20e67971a5 Use type EventsCacheCore instead of Vector#(7, Bit#(1)) 2021-09-02 16:10:55 +01:00
Franz Fuchs
9f615e4481 initial changes for HPM consistency 2021-09-02 14:50:17 +01:00
Robert Norton
0970951184 Fix decoding of lr / sc with explicit bounds. 
When decoding {lr,sc}.{b,h,w,d,c,q}.{ddc,cap} the IType was not being set correctly. For sc we also need to set the destination register.
 2021-09-01 10:16:49 +01:00
Peter Rugg
dbb6043760 Don't compile SelfInv* without define 2021-08-16 14:42:59 +01:00