Cheri-research/Toooba
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54d1a204f0fa0a7c2253802bd0bc4f65f7cfc543
Commit Graph

95 Commits

Author SHA1 Message Date
Jonathan Woodruff
54d1a204f0 Don't decode redirected streams until they are non-speculative. 2021-12-17 16:29:14 +00:00
Jonathan Woodruff
3322d1d3d7 Revert "An attempt at wiring up the specUpdate interface for the Btb." 
This reverts commit 022df36199.
 2021-12-16 12:10:50 +00:00
Jonathan Woodruff
022df36199 An attempt at wiring up the specUpdate interface for the Btb. 2021-12-15 18:40:58 +00:00
Jonathan Woodruff
4e0da006e8 Make non-speculative training optional. 
Removing non-speculative training actually improves performance in
CoreMark.  While it's "safer", I guess this isn't required for BSC.
 2021-11-24 17:11:36 +00:00
Jonathan Woodruff
7b472d4d3c Reduce area overhead by using an unguarded specfifo that does not have 
to be worst-case-sized, but can drop elements if it is full.
 2021-11-16 13:53:34 +00:00
Jonathan Woodruff
618dea1225 Feed head of RAS through to execute with training info to reset the head 
on a misprediction.
 2021-11-16 11:00:04 +00:00
Jonathan Woodruff
54c0ccadf0 Only train from branches that have all previous branches resolved. 2021-11-12 17:55:04 +00:00
Franz Fuchs
87977461a6 Merge branch 'CHERI' of github.com:CTSRD-CHERI/Toooba into CHERI 2021-09-29 14:23:20 +01:00
Franz Fuchs
db9b5c7f54 re-integrated TagController 2021-09-24 11:39:23 +01:00
Peter Rugg
8ef44b0a6c Workaround single step wedges by not waiting for flush before halting 2021-09-24 10:33:58 +00:00
Franz Fuchs
9320e53720 Bumped RISCV_HPM_Events made minor changes 2021-09-17 10:38:48 +01:00
Franz Fuchs
b25d70a8cc performed corrections for CONTRACTS_VERIFY 2021-09-07 08:15:03 +01:00
Franz Fuchs
4c9d89e936 Performed a bit of cleaning up 2021-09-06 13:33:13 +01:00
Franz Fuchs
e33b4021d8 Integrated generateHPMVector function 2021-09-03 17:37:43 +01:00
Franz Fuchs
20e67971a5 Use type EventsCacheCore instead of Vector#(7, Bit#(1)) 2021-09-02 16:10:55 +01:00
Franz Fuchs
9f615e4481 initial changes for HPM consistency 2021-09-02 14:50:17 +01:00
Franz Fuchs
cc25ee69d3 Check in Rename stage for nextPcs of Traps 2021-07-26 07:02:21 +01:00
Franz Fuchs
2831cd7ee3 Changed size of bags for testing SBC to 32 2021-07-16 14:51:26 +01:00
Franz Fuchs
4ba377366a Introduced new build flag for transient-execution testing contracts 2021-07-08 15:28:54 +01:00
Franz Fuchs
2eb2202acd Added checking for wild exceptions in MemExePipeline including adding an addtional port to the ROB for reading ppc/orig_inst 2021-06-28 07:34:57 +01:00
Franz Fuchs
fec16f64c8 Added first attempts for counting wild exceptions 2021-06-25 15:44:29 +01:00
Franz Fuchs
f83d7b1554 Added missing ifdefs 2021-06-24 08:35:21 +01:00
Franz Fuchs
0c80ac30bb Corrected wild jumps type to SupCnt 2021-06-23 15:36:45 +01:00
Franz Fuchs
76cdc13a50 Added counting code for return instructions 2021-06-22 18:01:32 +01:00
Franz Fuchs
06e0a3d810 corrected SBC jumps counting 2021-06-22 08:40:27 +01:00
Franz Fuchs
dce934500d Added counter mechanism for wild jumps 2021-06-11 10:47:15 +01:00
Franz Fuchs
c51af07278 Collect all architectural jump targets (the first 16) in a bag to enable verifying properties 2021-06-10 18:55:00 +01:00
Franz Fuchs
914eb17550 Added microarchitectural counter for renamed instructions 
This counter is used for the SBC Condition 1 verification
 2021-06-08 13:18:57 +01:00
jon
d7a492b48f Move to Flute standard placement for Tag Cache events, which is just the 
raw order from the CacheCore events.
 2021-06-01 15:17:25 +01:00
Franz Fuchs
ad044689cb added some of the performance counters in the L2 TLB 
- count L2 TLB accesses
- count L2 TLB misses
- count L2 TLB flushes
 2021-04-01 16:18:18 +01:00
Jonathan Woodruff
6ef565e56c Fix bugs in previous commit due to test build not using performance 
counters.
 2021-03-09 16:05:01 +00:00
jon
1ef2d0cbeb Include both execute redirect and commit redirect in "redirect" counter. 2021-03-09 15:57:15 +00:00
Peter Rugg
30e7090213 Multicore debug-module 2021-01-21 20:30:07 +00:00
Peter Rugg
e8487e2a1c Revert "Provide opt-in wedge debugging info" 
This reverts commit 68d3bd484e.
 2021-01-19 22:00:16 +00:00
Peter Rugg
20f1ddf587 Revert "Plumb through a lot more ROB debug state" 
This reverts commit 0f65994955.
 2021-01-19 21:40:59 +00:00
Peter Rugg
a6ab823d1d Revert "Cover interesting fetch and rename state for DEBUG_WEDGE configs" 
This reverts commit 5e9b478371.
 2021-01-19 21:39:59 +00:00
jon
f86d4d9dc0 Add counter support to ITLB. 2020-12-17 17:57:43 +00:00
jon
4ddcaff497 Support for data TLB counters. 2020-12-17 16:52:45 +00:00
jon
bab989d6d2 Support for stat counters from the tag controller. 
The order of the events is very not tested; 50% chance of being correct.
 2020-12-17 12:38:52 +00:00
jon
fa9931b64c Implement a couple Cache counters in the LLCache. 
These aren't too useful... We don't seem to have normal counters for
loads and stores in the baseline.
 2020-12-15 18:16:21 +00:00
jon
17a7a32092 Use DRegOR instead of immitating latching behaviour. 2020-12-15 16:18:36 +00:00
jon
b6a397df52 Support for ICache stat counters. 2020-12-15 14:49:16 +00:00
jon
73d25bf8f5 Support performance counters (hopefully) in the caches. The DCache 
should be fully wired up.
 2020-12-14 18:10:06 +00:00
jon
19a07882ab CSome style cleanups from chat with Alexandre. 2020-12-11 16:44:59 +00:00
jon
1bae03da9c Implement all the remaining core (not cache) memory stat counters. 2020-12-11 15:48:10 +00:00
jon
d6243be1dd Add a few more core performance counters. 2020-12-04 18:34:56 +00:00
jon
bdc2d494f2 Change name something that makes sense. 2020-12-04 17:12:26 +00:00
jon
4fcc18635a Supporting most architectural counters, wiring them out from 
CommitStage.
Also support multiple events per cycle.
 2020-12-02 15:28:41 +00:00
jon
259d34618c A design that actually passes one performance monitor trace from 
TestRig.  The example counted redirections, which happend to match
between Flute and Toooba for this example.
 2020-12-01 18:02:11 +00:00
Jonathan Woodruff
0289bfe17d Fix a couple errors due to changes somehow merged over from the rich_predicted_state branch. 2020-11-09 11:14:11 +00:00