Cheri-research/Toooba
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913 Commits 7 Branches 0 Tags
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Commit Graph

497 Commits

Author SHA1 Message Date
Karlis Susters
1123f43423 Config for L1D Markov-2-Bigtable 2023-03-20 13:04:21 +00:00
Karlis Susters
e584786c93 Bugfix to Stride Adaptive config 2023-03-17 11:26:23 +00:00
Karlis Susters
cef4990ce3 Implement adaptive stride prefetcher, update prefetcher tests 2023-03-17 10:58:54 +00:00
Karlis Susters
65ed55cb8a Cleanup: remove non-BRAM prefetchers 2023-03-16 12:29:06 +00:00
Karlis Susters
9c4da78c34 Modifications and config for L1LL Markov-2 prefetcher 2023-03-16 11:55:27 +00:00
Karlis Susters
239e011adf Config for L1D Stride-2-BigTable 2023-03-15 16:30:35 +00:00
Karlis Susters
8617d38e80 Config for L1D Stride-2 prefetcher 2023-03-14 13:52:17 +00:00
Karlis Susters
ada7d133e4 Config for L1D Stride-4 prefetcher 2023-03-13 14:51:59 +00:00
Karlis Susters
54b9f6669e Bugfix for L1LL D prefetchers, config for L1LL D Stride-3 2023-03-08 13:37:04 +00:00
Karlis Susters
30a3aff5af Config for L1D Stride-3 prefetcher 2023-03-07 12:33:51 +00:00
Karlis Susters
a52a36e199 Push config for L1LL I Single window-2 prefetcher 2023-03-02 15:42:37 +00:00
Karlis Susters
1d2affc707 Set up config for L1I single window-2 prefetcher 2023-03-01 17:20:19 +00:00
Karlis Susters
6509cf6445 Changed config to L1D Block-1 prefetcher and fixed potential bug 2023-02-28 12:29:38 +00:00
Karlis Susters
e228854d9f Change config to next-1-line L1I prefetcher 2023-02-22 17:08:48 +00:00
Karlis Susters
87a88a749b Set up config for next-2-lines on miss L1I prefetcher 2023-02-21 10:45:56 +00:00
Karlis Susters
bd2ceec15f L1D prefetch into S, not M 2023-02-20 11:17:59 +00:00
Karlis Susters
2c9428d1f3 Prepared repo for building on FPGA 2023-02-13 21:52:50 +00:00
Karlis Susters
9d027a3f4b Implemented BRAM versions of stride, target, markov prefetchers 2023-02-13 11:59:26 +00:00
Karlis Susters
31ae938e78 Implemented a stride prefetcher with BRAM instead of vectors 2023-02-13 11:59:26 +00:00
Karlis Susters
79c55c5651 Implemented cross cache prefetching, fixed some coherence bugs in LLC 2023-02-13 11:59:26 +00:00
Karlis Susters
dca4b980c5 Implemented a markov chain data prefetcher 2023-02-13 11:59:26 +00:00
Karlis Susters
9f733eddf1 Merged reportHit & reportMiss, changed compile time parameter passing 2023-02-13 11:59:26 +00:00
Karlis Susters
06e648df6a Implemented target table module, refactored single and multi window instruction prefetchers to use it 2023-02-13 11:59:26 +00:00
Karlis Susters
7c05ebbd90 Implemented multi line target prefetcher 2023-02-13 11:59:26 +00:00
Karlis Susters
e602d4780e LLC prefetcher fixes and single window target prefetcher implementation 2023-02-13 11:59:26 +00:00
Karlis Susters
347107b733 Prefetcher implementation in both L1 and LL and data logging 2023-02-13 11:59:26 +00:00
Peter Rugg
6931201a14 Avoid wedge on repeated debug resumes (with jdw57 and aj443) 
ConfigReg avoids a compile error
 2023-01-31 21:02:17 +00:00
Peter Rugg
e120b3427d Merge branch 'LoadTagsImprove' into CHERI 2022-11-14 13:28:44 +00:00
Franz Fuchs
de0e19ca55 added do not cares for missing struct fields in ROB 2022-10-21 09:22:31 +00:00
Alexandre Joannou
d068df3bd8 uncomment a verbosity check 2022-09-02 12:37:07 +00:00
Jonathan Woodruff
1fceb8fa72 Use standard imports as the fixes have been upstreamed. 2022-08-15 16:18:23 +00:00
Alexandre Joannou
947cf8ed7b NonPipelined API update 2022-08-15 16:18:23 +00:00
Alexandre Joannou
e4bdbfc98a Bump BlueStuff + add outter subordinate trafic as master to internal bus 2022-08-15 16:18:23 +00:00
Alexandre Joannou
a954fd5b38 Use NonPipelined dividers + update "reset_by" in CoreW 2022-08-15 16:18:23 +00:00
gameboo
45135a0bee Don't assume a XILINX tool flow 2022-08-15 16:18:23 +00:00
Jonathan Woodruff
8cb96bae5c Fixes for load address tracing. 2022-08-12 15:09:01 +00:00
Franz Fuchs
2f595167a4 commented out debug print statements in Ras.bsv 2022-07-29 15:41:28 +01:00
Franz Fuchs
e89af4a66d added typedefs to STLPred 2022-07-26 09:18:20 +01:00
Franz Fuchs
d3e8ef8d90 removed unnecessary declarations in RenameStage 2022-07-25 13:18:50 +01:00
Jonathan Woodruff
a1065616e0 Fix tracing of writes to MMIO addresses. 2022-07-22 15:37:25 +00:00
Franz Fuchs
502e64c24b fixed not defined warning in ConnectalBramFifo 2022-07-11 15:11:59 +01:00
Franz Fuchs
4abf838d62 implemented missing notFull method in SpecFifo 2022-07-11 14:56:30 +01:00
Franz Fuchs
ad9f2cab3d used RVFI defines as declared in ToReorderBuffer 2022-07-11 14:18:19 +01:00
Alexandre Joannou
9960d67ed8 Removed some debug print statements 2022-07-11 11:55:40 +00:00
Franz Fuchs
c85b13c5af added MELTDOWN_CF ifdef and enabled it 2022-06-30 12:55:53 +01:00
Peter Rugg
fb259583dc Attempt to clear tag on exception path before forwarding. 
This is likely to be bad for timing, but might just work at 25MHz.
 2022-06-15 00:53:55 +01:00
Franz Fuchs
f8b97ceb6a corrected ifdef in STLPred.bsv 2022-06-09 15:24:10 +01:00
Franz Fuchs
b79a228093 added no prediction STL predictor 2022-06-08 12:23:35 +01:00
Franz Fuchs
891567f3aa added STL predictor module and moved state from SplitLSQ to it 2022-06-08 12:04:25 +01:00
Peter Rugg
b113d05095 Prioritise misaligned over RVFIDII load access fault 2022-05-18 14:59:43 +01:00