Cheri-research/Toooba
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Commit Graph

173 Commits

Author SHA1 Message Date
gameboo
9657339d87 "fix" non PERFORMANCE_MONITORING build 2021-09-29 18:09:06 +01:00
Franz Fuchs
87977461a6 Merge branch 'CHERI' of github.com:CTSRD-CHERI/Toooba into CHERI 2021-09-29 14:23:20 +01:00
Franz Fuchs
cf8bfdc4a8 Merge branch 'faf28_hpm_consistency' into CHERI 2021-09-29 14:04:08 +01:00
Franz Fuchs
db9b5c7f54 re-integrated TagController 2021-09-24 11:39:23 +01:00
Peter Rugg
8ef44b0a6c Workaround single step wedges by not waiting for flush before halting 2021-09-24 10:33:58 +00:00
Franz Fuchs
9ea66bed86 Merge pull request #18 from CTSRD-CHERI/faf28_hpm_consistency 
Using HPM information from one central struct
 2021-09-20 13:21:52 +01:00
Franz Fuchs
9320e53720 Bumped RISCV_HPM_Events made minor changes 2021-09-17 10:38:48 +01:00
Jonathan Woodruff
c489a177d4 Fix type error. 2021-09-08 10:23:29 -05:00
Jonathan Woodruff
08231b7e5c Hopefully don't wedge on ifetch bus error. 
We think that we were wedging on IFetch bus error.
It appears that we didn't make the last instruction fragment valid in the bus error case, and expect that this path was not previously exercised.
This change returns 0s (to hopefully make the error less subtle) in exactly the right number of fragments.
 2021-09-08 10:11:25 -05:00
Franz Fuchs
b25d70a8cc performed corrections for CONTRACTS_VERIFY 2021-09-07 08:15:03 +01:00
Franz Fuchs
bc7eed67ab Did more cleaning up 2021-09-06 15:55:28 +01:00
Franz Fuchs
4c9d89e936 Performed a bit of cleaning up 2021-09-06 13:33:13 +01:00
Franz Fuchs
e33b4021d8 Integrated generateHPMVector function 2021-09-03 17:37:43 +01:00
Franz Fuchs
61d788ebc7 define No_Of_Evts in StatCounters 2021-09-03 14:14:32 +01:00
Franz Fuchs
20e67971a5 Use type EventsCacheCore instead of Vector#(7, Bit#(1)) 2021-09-02 16:10:55 +01:00
Franz Fuchs
9f615e4481 initial changes for HPM consistency 2021-09-02 14:50:17 +01:00
Franz Fuchs
cc25ee69d3 Check in Rename stage for nextPcs of Traps 2021-07-26 07:02:21 +01:00
Franz Fuchs
2831cd7ee3 Changed size of bags for testing SBC to 32 2021-07-16 14:51:26 +01:00
Franz Fuchs
c37c611522 Merge branch 'CHERI' into faf28_sbc_jumps 2021-07-08 17:14:27 +01:00
Franz Fuchs
4ba377366a Introduced new build flag for transient-execution testing contracts 2021-07-08 15:28:54 +01:00
Franz Fuchs
2eb2202acd Added checking for wild exceptions in MemExePipeline including adding an addtional port to the ROB for reading ppc/orig_inst 2021-06-28 07:34:57 +01:00
Franz Fuchs
fec16f64c8 Added first attempts for counting wild exceptions 2021-06-25 15:44:29 +01:00
Franz Fuchs
f83d7b1554 Added missing ifdefs 2021-06-24 08:35:21 +01:00
Franz Fuchs
0c80ac30bb Corrected wild jumps type to SupCnt 2021-06-23 15:36:45 +01:00
Franz Fuchs
76cdc13a50 Added counting code for return instructions 2021-06-22 18:01:32 +01:00
Franz Fuchs
06e0a3d810 corrected SBC jumps counting 2021-06-22 08:40:27 +01:00
Peter Rugg
4a50ae5bc8 Fix some misplaced ifdefs 2021-06-14 15:13:35 +01:00
Franz Fuchs
dce934500d Added counter mechanism for wild jumps 2021-06-11 10:47:15 +01:00
Franz Fuchs
c51af07278 Collect all architectural jump targets (the first 16) in a bag to enable verifying properties 2021-06-10 18:55:00 +01:00
Franz Fuchs
914eb17550 Added microarchitectural counter for renamed instructions 
This counter is used for the SBC Condition 1 verification
 2021-06-08 13:18:57 +01:00
jon
4ae9f5346c Merge branch 'CHERI' of https://github.com/CTSRD-CHERI/Toooba into CHERI 2021-06-01 15:18:29 +01:00
jon
d7a492b48f Move to Flute standard placement for Tag Cache events, which is just the 
raw order from the CacheCore events.
 2021-06-01 15:17:25 +01:00
Peter Rugg
f909d886c9 Add a copyright 2021-05-27 14:45:15 +01:00
Peter Rugg
1b5f4ee9e0 Add capability-aware compressed decoding 2021-05-26 16:25:55 +01:00
Franz Fuchs
d78a2799d3 Fixed small mistake pointed out by Peter(pdr32) 2021-05-12 10:46:07 +01:00
Franz Fuchs
fcea3a1f4e included suggestions from Peter (pdr32) 2021-05-11 19:28:49 +01:00
Franz Fuchs
f6bd0b0e1b first attempts to fix inhibit mismatch 2021-05-11 14:13:02 +01:00
Peter Rugg
0a7e77230e Style improvements (suggested by jrtc27) 2021-05-05 13:32:07 +01:00
Peter Rugg
005ba1bd6f Add LoadCapPageFault exception cases 2021-04-29 16:02:30 +01:00
Peter Rugg
3b07a2a17c Add revocation 3.0 bits 2021-04-29 16:02:30 +01:00
Nathaniel Filardo
55da2986af Set mtval for excStoreCapPageFault-s correctly 
These were previously defaulting to 0, deeply confusing the kernel.
 2021-04-26 02:07:10 +01:00
Peter Rugg
fcea5365f6 Initial implementation CLoadTags 
This currently just loads in the data on cache miss, so won't help to reduce DRAM overhead, but will be forwards compatible and save on instructions in the revoker loop.
 2021-04-08 17:08:15 +01:00
Franz Fuchs
ad044689cb added some of the performance counters in the L2 TLB 
- count L2 TLB accesses
- count L2 TLB misses
- count L2 TLB flushes
 2021-04-01 16:18:18 +01:00
Jonathan Woodruff
6ef565e56c Fix bugs in previous commit due to test build not using performance 
counters.
 2021-03-09 16:05:01 +00:00
jon
1ef2d0cbeb Include both execute redirect and commit redirect in "redirect" counter. 2021-03-09 15:57:15 +00:00
jon
89f0c3a45f Reduce verbosity. 2021-03-05 12:11:49 +00:00
Peter Rugg
7a1d234e40 Merge branch 'ifetch-cleanup' into CHERI 2021-03-02 11:57:31 +00:00
Peter Rugg
9f0968b1cb Fix AXI_Size=16 for MMIO of caps 2021-02-19 17:19:47 +00:00
jon
0f3fd15d41 Initial implementation of map of HPM counters into supervisor and user 
mode.  This version just unconditionally exposes them.
 2021-02-17 17:07:53 +00:00
Alexandre Joannou
4c19a34eda Workaround for scheduling issues when using PERFORMANCE_MONITORING (with jdw57) 2021-02-15 18:07:08 +00:00