Karlis Susters
d2b41c852d
Added prefetcher port to ICrqmshr and retired prefetchRqDone
2023-04-12 21:55:13 +03:00
Karlis Susters
bf0f26ce56
Implemented double target table and the corresponding markov prefetcher
2023-04-12 21:52:56 +03:00
Karlis Susters
2d94cba951
Implemented vector prefetcher setup in L2
2023-04-12 21:50:31 +03:00
Karlis Susters
4ea9b17971
Minor changes to targettable and instruction target prefetchers
2023-04-12 21:31:08 +03:00
Karlis Susters
1ad1dfad6a
Config for MarkovOnHit-2-8KiB.
2023-03-30 13:07:34 +01:00
Karlis Susters
625dbb3066
Count sent prefetch requests as Store misses, cache full cycles as stores
2023-03-30 13:06:12 +01:00
Karlis Susters
06651f1a31
Actually repurpose L1D store count, not store miss count
2023-03-24 15:15:03 +00:00
Karlis Susters
7d7d38ad49
Repurpose L1D store miss count to track number of cycles cache is full
2023-03-24 15:11:08 +00:00
Karlis Susters
a4ad28d865
Config for MarkovOnHit-1-bigtable
2023-03-23 11:09:36 +00:00
Karlis Susters
643afd81e2
Implementation and config for L1D StrideV2-2 prefetcher
2023-03-22 22:12:59 +00:00
Karlis Susters
808d961a7b
Implementation and config for L1D MarkovOnHit-2-BigTable
2023-03-21 19:26:38 +00:00
Karlis Susters
1123f43423
Config for L1D Markov-2-Bigtable
2023-03-20 13:04:21 +00:00
Karlis Susters
e584786c93
Bugfix to Stride Adaptive config
2023-03-17 11:26:23 +00:00
Karlis Susters
cef4990ce3
Implement adaptive stride prefetcher, update prefetcher tests
2023-03-17 10:58:54 +00:00
Karlis Susters
65ed55cb8a
Cleanup: remove non-BRAM prefetchers
2023-03-16 12:29:06 +00:00
Karlis Susters
9c4da78c34
Modifications and config for L1LL Markov-2 prefetcher
2023-03-16 11:55:27 +00:00
Karlis Susters
239e011adf
Config for L1D Stride-2-BigTable
2023-03-15 16:30:35 +00:00
Karlis Susters
8617d38e80
Config for L1D Stride-2 prefetcher
2023-03-14 13:52:17 +00:00
Karlis Susters
ada7d133e4
Config for L1D Stride-4 prefetcher
2023-03-13 14:51:59 +00:00
Karlis Susters
54b9f6669e
Bugfix for L1LL D prefetchers, config for L1LL D Stride-3
2023-03-08 13:37:04 +00:00
Karlis Susters
30a3aff5af
Config for L1D Stride-3 prefetcher
2023-03-07 12:33:51 +00:00
Karlis Susters
a52a36e199
Push config for L1LL I Single window-2 prefetcher
2023-03-02 15:42:37 +00:00
Karlis Susters
1d2affc707
Set up config for L1I single window-2 prefetcher
2023-03-01 17:20:19 +00:00
Karlis Susters
6509cf6445
Changed config to L1D Block-1 prefetcher and fixed potential bug
2023-02-28 12:29:38 +00:00
Karlis Susters
e228854d9f
Change config to next-1-line L1I prefetcher
2023-02-22 17:08:48 +00:00
Karlis Susters
87a88a749b
Set up config for next-2-lines on miss L1I prefetcher
2023-02-21 10:45:56 +00:00
Karlis Susters
bd2ceec15f
L1D prefetch into S, not M
2023-02-20 11:17:59 +00:00
Karlis Susters
2c9428d1f3
Prepared repo for building on FPGA
2023-02-13 21:52:50 +00:00
Karlis Susters
9d027a3f4b
Implemented BRAM versions of stride, target, markov prefetchers
2023-02-13 11:59:26 +00:00
Karlis Susters
31ae938e78
Implemented a stride prefetcher with BRAM instead of vectors
2023-02-13 11:59:26 +00:00
Karlis Susters
79c55c5651
Implemented cross cache prefetching, fixed some coherence bugs in LLC
2023-02-13 11:59:26 +00:00
Karlis Susters
dca4b980c5
Implemented a markov chain data prefetcher
2023-02-13 11:59:26 +00:00
Karlis Susters
9f733eddf1
Merged reportHit & reportMiss, changed compile time parameter passing
2023-02-13 11:59:26 +00:00
Karlis Susters
06e648df6a
Implemented target table module, refactored single and multi window instruction prefetchers to use it
2023-02-13 11:59:26 +00:00
Karlis Susters
7c05ebbd90
Implemented multi line target prefetcher
2023-02-13 11:59:26 +00:00
Karlis Susters
e602d4780e
LLC prefetcher fixes and single window target prefetcher implementation
2023-02-13 11:59:26 +00:00
Karlis Susters
347107b733
Prefetcher implementation in both L1 and LL and data logging
2023-02-13 11:59:26 +00:00
Peter Rugg
8ba929438d
Fix cloadtags in LLC
2022-03-31 02:07:01 +01:00
Peter Rugg
6d4644ce73
Add tag-only state to MESI and interface with tagOnlyReq of tag controller
2022-03-31 02:07:01 +01:00
Franz Fuchs
bc7eed67ab
Did more cleaning up
2021-09-06 15:55:28 +01:00
Franz Fuchs
9f615e4481
initial changes for HPM consistency
2021-09-02 14:50:17 +01:00
Peter Rugg
dbb6043760
Don't compile SelfInv* without define
2021-08-16 14:42:59 +01:00
Peter Rugg
10f0807a9b
Fix arbitration for non-power-of-two numbers of sources
2021-05-28 14:37:24 +01:00
Peter Rugg
bf911326e3
Fix some arbitration bugs
2021-05-28 12:36:06 +01:00
Jessica Clarke
46b1519cb0
mkXBar: Simplify as fallback case handles priority case correctly
...
The first element in the vector will be srcRR[dst], so the special case
is unnecessary.
2021-05-28 02:57:12 +01:00
Jessica Clarke
afd636a0f5
mkXBar: Fix bias towards earlier sources
...
In the case where the prioritised round-robin source does not have a
request, this was always picking the earliest source that had one, which
means if some sources are making more requests than others (e.g. there
is lots of D$ churn but the I$ has a high hit rate) then, whilst the
cycles where srcRR[dst] prioritises a source that is making requests are
fair, the cycles where it prioritises a source that is not making
requests is not fair, since then the earlier sources will be
prioritised. Instead, make the fallback priority similarly dynamic so we
cycle through the order we look at the sources in.
2021-05-28 02:32:04 +01:00
jon
86afb7e68e
Add counter for LL writebacks (in the ST_MISS field).
2021-04-12 16:21:58 +01:00
Peter Rugg
fcea5365f6
Initial implementation CLoadTags
...
This currently just loads in the data on cache miss, so won't help to reduce DRAM overhead, but will be forwards compatible and save on instructions in the revoker loop.
2021-04-08 17:08:15 +01:00
jon
8da520175f
Use an (unguarded) BRAM in the Btb.
...
Also, assume that a target that is not taken should be removed from the
Btb. (The read that checked isn't possible with BRAM timing unless we
latched and had an extra port, but removing the check actually improved
performance a bit in CoreMark, and the pipeline should actually only be
reporting a non-taken branch if we did something wrong.)
2021-03-06 07:19:50 +00:00
jon
fa9931b64c
Implement a couple Cache counters in the LLCache.
...
These aren't too useful... We don't seem to have normal counters for
loads and stores in the baseline.
2020-12-15 18:16:21 +00:00
