Cheri-research/Toooba
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45 Commits

Author SHA1 Message Date
Akilan
8097b5cd3d enabled performance counters 2026-01-27 15:34:53 +00:00
Samuel Stark
02ee2bdee0 Move RVFI toggle into Include_RISCY_Config.mk 
Previously, Makefiles had to add new include paths and -D defines manually when they wanted to include RVFI.
This caused hard-to-diagnose errors in repositories consuming Toooba that expected -D RVFI to work.
This commit makes Include_RISCY_Config.mk take an optional make-variable argument RVFI, which defaults to "false", and adds the relevant paths and -D defines if it is set to "true".
This does not cover RVFI_DII, which is a simulation-only extension to allow instruction injection.
This commit also includes fixes to the Makefiles in ./builds/ to use this interface properly.
 2024-06-03 15:51:48 +01:00
Jonathan Woodruff
1b9d498e95 Standardise on using underscores in directory names in makefiles. 2024-05-17 11:21:42 +01:00
Jonathan Woodruff
2c648eb1ed Restructure makefiles so that all common and branch-specific flags/files 
are in Include_RISCY_Config.mk so that this can be included from an
external repo without replicating Toooba branch-specific flags in that
repo.
 2024-05-15 10:01:28 +01:00
Jonathan Woodruff
d29bdf0a81 Default to Data Cache Stride 2 prefetcher, and no Instruction Cache 
prefetcher.
 2023-05-17 16:50:42 +00:00
Karlis Susters
0554fad990 Config for L1D MarkovDouble 2023-04-25 13:05:01 +01:00
Karlis Susters
73e710d875 Config for L1I 1window-target-1 2023-04-22 10:04:05 +01:00
Karlis Susters
4bc04b581d Config for L1I MultiWindowTarget-2 2023-04-19 14:22:01 +03:00
Karlis Susters
bf0f26ce56 Implemented double target table and the corresponding markov prefetcher 2023-04-12 21:52:56 +03:00
Karlis Susters
d6b54be882 Config for no-prefetcher baseline 2023-04-04 11:30:01 +03:00
Karlis Susters
1ad1dfad6a Config for MarkovOnHit-2-8KiB. 2023-03-30 13:07:34 +01:00
Karlis Susters
96bed3532e Config for L1D StrideV2-2 prefetcher 2023-03-24 15:11:39 +00:00
Karlis Susters
a4ad28d865 Config for MarkovOnHit-1-bigtable 2023-03-23 11:09:36 +00:00
Karlis Susters
643afd81e2 Implementation and config for L1D StrideV2-2 prefetcher 2023-03-22 22:12:59 +00:00
Karlis Susters
808d961a7b Implementation and config for L1D MarkovOnHit-2-BigTable 2023-03-21 19:26:38 +00:00
Karlis Susters
1123f43423 Config for L1D Markov-2-Bigtable 2023-03-20 13:04:21 +00:00
Karlis Susters
fe95337a97 Add STRIDE_ADAPTIVE to makefile 2023-03-20 11:41:03 +00:00
Karlis Susters
15b9243f9a Set up config for L1D StrideAdaptive prefetcher 2023-03-17 11:26:49 +00:00
Karlis Susters
9c4da78c34 Modifications and config for L1LL Markov-2 prefetcher 2023-03-16 11:55:27 +00:00
Karlis Susters
ada7d133e4 Config for L1D Stride-4 prefetcher 2023-03-13 14:51:59 +00:00
Karlis Susters
54b9f6669e Bugfix for L1LL D prefetchers, config for L1LL D Stride-3 2023-03-08 13:37:04 +00:00
Karlis Susters
30a3aff5af Config for L1D Stride-3 prefetcher 2023-03-07 12:33:51 +00:00
Karlis Susters
76c0071c9e Config for L1LL D Block-1 prefetcher 2023-03-03 14:23:13 +00:00
Karlis Susters
a52a36e199 Push config for L1LL I Single window-2 prefetcher 2023-03-02 15:42:37 +00:00
Karlis Susters
1d2affc707 Set up config for L1I single window-2 prefetcher 2023-03-01 17:20:19 +00:00
Karlis Susters
6509cf6445 Changed config to L1D Block-1 prefetcher and fixed potential bug 2023-02-28 12:29:38 +00:00
Karlis Susters
7a352d774e Set up config for an L2 next-2-line-on-miss instruction prefetcher 2023-02-24 11:43:29 +00:00
Karlis Susters
5cb283a5d5 Set up config for L1D block prefetcher 2023-02-23 10:30:47 +00:00
Karlis Susters
87a88a749b Set up config for next-2-lines on miss L1I prefetcher 2023-02-21 10:45:56 +00:00
Karlis Susters
42777725bf Random update change 2023-02-20 15:47:24 +00:00
Karlis Susters
9ac29f4e11 Enable only L1D block prefetcher 2023-02-20 11:03:49 +00:00
Karlis Susters
56035b1ce4 Changed prefetcher configuration 2023-02-16 14:01:50 +00:00
Karlis Susters
7ac5ed5efd Change config to simpler one 2023-02-14 16:47:06 +00:00
Karlis Susters
2c9428d1f3 Prepared repo for building on FPGA 2023-02-13 21:52:50 +00:00
Jessica Clarke
17ed2dfde8 Revert CACHE_SIZE back to LARGE 
The default was erroneously changed, causing P3 builds to have smaller
caches, so switch it back. The RVFI-DII builds override this with a TEST
configuration anyway now.
 2020-07-05 21:44:17 +01:00
Jessica Clarke
0b0b863baa Replace home-grown dependency script with Bluespec-provided makedepend.tcl 
This one has the advantage of being able to be called with the same
flags as bsc, rather than needing to pass things through special
environment variables. As a result, revert all our changes to dealing
with BSC_COMPILATION_FLAGS (some of this diff therefore looks strangely
formatted, but it's to match upstream verbatim, and should be left that
way to minimise diffs and avoid conflicts).
 2020-07-05 21:26:18 +01:00
jon
8ae5d3a1b2 Build RVFI_DII Toooba with very small caches, 2-way set associative to 
maximise cache and memory verification.
 2020-05-28 10:59:08 +01:00
Alexandre Joannou
370ed61bc4 Integrate the generation of dependenices to Makefiles 2020-04-23 14:55:28 +01:00
Jonathan Woodruff
3a79b022ea Merge branch 'master' into RVFI_DII, a complex merge for the fetch stage! 2020-03-18 11:35:59 +00:00
Jonathan Woodruff
909423e8e8 Use smaller L2 size (256KiB) for TestRIG. 2019-12-13 13:00:52 +00:00
Niraj Nayan Sharma
601bbe5a82 No longer using Xilinx FPU modules 2019-12-14 12:44:02 +05:30
rsnikhil
666dd2ad92 Small tweak to remove unnecessary explicit boot rom addrs (subsumed by IO) 2019-04-22 15:12:30 -04:00
rsnikhil
51bdff05d8 Updated Run_regression.py to utilize parallel processes 2019-04-18 18:42:06 -04:00
rsnikhil
47985fa93f Updated Makefiles so in src_SSITH_P3, RTL refers to Xilinx FP RTL instead of simulation models 2019-04-04 13:10:45 -04:00
rsnikhil
ee24a93944 Initial load of files 2019-03-26 14:49:40 -04:00