86e143a9f7
Changes that are much more likely to work for uncached memory accesses, up to 128-bits. I'm getting a lockup in simulation that I haven't resolved yet, but the request looks ok.
jon
2020-06-24 19:45:34 +01:00
312d0316da
Use updated Bluestuff library, and also support uncached 128-bit transactions through MMIO.
jon
2020-06-24 11:57:43 +01:00
56cd502145
Bump bluestuff to recent version. This needs updates to the source.
jon
2020-06-24 11:55:12 +01:00
a51ddf17be
Use the request ID in the response to the DMA interface.
jon
2020-06-20 12:15:00 +01:00
7d866f85e7
Regenerate verilog
Peter Rugg
2020-06-17 13:02:20 +01:00
8778369fe5
Merge remote-tracking branch 'upstream/master' into CHERI
Peter Rugg
2020-06-17 13:01:41 +01:00
49a9e5fc64
Remove unconnected signal in simulation
Peter Rugg
2020-06-17 11:43:28 +01:00
0e7df46dce
Allow read/write of dpc
Peter Rugg
2020-06-17 11:42:58 +01:00
4f4bbbbdcb
Add new TagController parameters to synth makefile
Peter Rugg
2020-06-17 11:40:23 +01:00
dcfdb34f0a
Changes to build with the now more parameterisable TagController.
jon
2020-06-15 16:46:15 +01:00
ad66967916
Bump capability library to version with fixed mask calculation.
jon
2020-06-12 17:21:26 +01:00
d35cea017e
Bump to version allowing multiple outstanding requests.
jon
2020-06-12 17:19:46 +01:00
e08e97c17b
Use the 80000000 entry point for RVFI_DII.
jon
2020-06-11 15:59:19 +01:00
6719925b78
Fetch initial instructions from boot rom in simulation to improve testing. To make this not fail, remove the reset server behaviour in SoC_Top which appears to not be needed as it is only calling reset servers upon actual reset when everything has been reset anyway. I suppose these reset servers are meant for debug-unit-initiated reset events.
jon
2020-06-11 10:56:07 +01:00
1de6fc941e
Adjust debug output to always print certain portions as this is more useful.
jon
2020-06-11 09:47:19 +01:00
c96021e5f2
Just fall through to default when the upper bits are not as expected to avoid lockup, though it may lockup anyway. We should respond with a bus error or something instead.
jon
2020-06-11 09:45:38 +01:00
f582d6550b
Add BLUESIM to two simulation builds as the TagController expects this variable to be set when building for simulation.
jon
2020-06-11 09:43:38 +01:00
8492136abd
Attempt to convert more functions in the MMIO platform to respect the alignment of the original data. Also eliminate the call to the reimplementation of the AMO functions. (One call was already converted to use the common function, and I've now converted the other.) It's honestly unknown how much of this works, but it's more likely to work than what was previously implemented, I think, given that the previou implementation was based on some basic misconceptions concerning data alignment.
jon
2020-06-09 17:39:36 +01:00
4b3f97cb6a
More correct version of select function. Also the beginnings of a select function for writes which is not yet used.
jon
2020-06-09 12:33:43 +01:00
122e98b0c7
Attempt to provide correct alignment for MMIO requests in flits returned to bus. This does not yet attempt to fix writes which might likely also need fixing.
jon
2020-06-08 19:03:12 +01:00
3117fcc9d5
Regenerate verilog
Peter Rugg
2020-06-07 16:47:54 +01:00
4fbabae1dd
component.xml fixes for synthesis
Peter Rugg
2020-06-07 16:47:38 +01:00
9ec9b34376
Don't overwrite earlier exception in Execute.
jon
2020-06-06 09:42:11 +01:00
0fa18c6b1f
Bump TagController to version that builds.
jon
2020-06-06 09:40:48 +01:00
afe61b0626
Bump tagcontroller to version which implements/optimises burst writes.
jon
2020-06-05 19:34:13 +01:00
be2c92b291
Regenerate verilog
Peter Rugg
2020-06-05 17:49:32 +01:00
e579f895dc
CPU_Decode_C.bsv: Sync from Flute
Jessica Clarke
2020-06-03 18:14:58 +01:00
962ade1092
Fixes for synthesis
Peter Rugg
2020-06-05 17:40:28 +01:00
db0e357475
Merge pull request #16 from jrtc27/compressed-fp-load-store
Rishiyur S. Nikhil
2020-06-04 08:26:09 -04:00
046319b909
Remove Tandem verification
Peter Rugg
2020-06-03 22:18:33 +01:00
1d12a97741
CPU_Decode_C.bsv: Sync from Flute
Jessica Clarke
2020-06-03 18:14:58 +01:00
f3a8fc44f5
Bump cheri-cap-lib
Peter Rugg
2020-06-03 12:44:13 +01:00
9aeb8f1ea9
Fix CSR read immediate case
Peter Rugg
2020-06-02 20:50:56 +01:00
7612738ff5
Changes needed for working TagController in Toooba.
jon
2020-06-02 19:05:56 +01:00
bb3eddccf2
Implement cap_mode switch for legacy loads and stores, as the mechanism for decoding has changed and was not setting the new flag.
jon
2020-06-02 19:00:28 +01:00
73a8b99c6c
Bump cheri-cap-lib
Peter Rugg
2020-06-02 10:22:36 +01:00
078d39b9df
Enable write bursts in LLC AXI4 adapter.
jon
2020-06-02 09:40:37 +01:00
9bbd8dc872
Bump the tag controller version to the one needed for Toooba.
jon
2020-06-02 09:31:45 +01:00
675de23dc2
Fix TestSubset top check the wrong way around
Peter Rugg
2020-06-01 20:23:42 +01:00
b7c73d4422
Link offset in JAL
Peter Rugg
2020-06-01 18:57:51 +01:00
1725cdda8f
Fix bug where immediate discarded too early in Scr case
Peter Rugg
2020-06-01 15:12:30 +01:00
f7deb7349b
Fix writeback when reading and writing CSR/SCR together
Peter Rugg
2020-06-01 15:04:59 +01:00
16eac986ef
Fix EPC/MTVEC updates ignoring old value
Peter Rugg
2020-06-01 12:17:14 +01:00
6a8f0e5bc0
Rename 'cap-mode' in Mem pipeline to ddc offset, since explicit memory instructions contradicting the cap_mode exist
Peter Rugg
2020-05-29 17:05:03 +01:00
a7d4d8e4a4
Fix bug where explicit cap-rel mem accesses would always trap as untagged
Peter Rugg
2020-05-29 16:43:20 +01:00
4b4b5836e8
Populate tval with CHERI trap information
Peter Rugg
2020-05-29 13:27:23 +01:00
a49d3d2b6b
Add ASR restrictions
Peter Rugg
2020-05-28 23:25:20 +01:00
ffeed959a3
Believed-to-be-working attaching of tags to write bursts in the AXI4 LLC wrapper.
jon
2020-05-28 18:21:03 +01:00
8ae5d3a1b2
Build RVFI_DII Toooba with very small caches, 2-way set associative to maximise cache and memory verification.
jon
2020-05-28 10:59:08 +01:00
8a07e18439
Do memory zeroing on reset when doing RVFI-DII. I couldn't quite use the implementation from Flute as the register was too wide for verilator. This one uses wide memories instead, which is way complicated, but I think it works. The width of the memory can be traded off for reset speed. The width at the moment is 8192 bits, which seems to be fast enough.
jon
2020-05-28 10:55:46 +01:00
57129f6383
Some minor cleanup of decode
Peter Rugg
2020-05-21 15:51:03 +01:00
2702f40b5e
Initial implementation of CSetBoundsExact
Peter Rugg
2020-05-21 15:50:37 +01:00
791e862377
Initial (slow) implementation of CTestSubset
Peter Rugg
2020-05-21 15:49:25 +01:00
0a84227f93
Implement DDC offset.
jon
2020-05-20 18:03:14 +01:00
d00ade6c9d
Fix new-write-folding-in function to copy original tags where there are no byte-enables set.
jon
2020-05-20 13:31:09 +01:00
072c188f92
Initial implementation of CCSeal
Peter Rugg
2020-05-19 23:05:18 +01:00
61b97e090d
Fix CFromPtr common case
Peter Rugg
2020-05-19 23:04:53 +01:00
372e4e4dfb
Bump BSV-RVFI-DII
Peter Rugg
2020-05-19 16:36:59 +01:00
e74220afc4
Implement CFromPtr
Peter Rugg
2020-05-19 02:37:53 +01:00
cd4d296a0c
Initial attempt to allow reads/writes to xtvec, xepc via xtcc, xepcc
Peter Rugg
2020-05-14 17:22:32 +01:00
82498cd963
Only unseal next_pc after exception checks have been made.
jon
2020-05-13 12:48:23 +01:00
7c0dad18d6
Deal with separate kinds of sealing more explicitly
Peter Rugg
2020-05-13 11:42:57 +01:00
a6fd7acf3e
Temporary resolution of signExtension behaviour for getType. Peter intends to use getKind from an updated version of cheri-cap-lib.
jon
2020-05-12 17:25:44 +01:00
0f0d1a983b
Remove references to ScrFile which were mysteriously still here.
jon
2020-05-12 17:24:50 +01:00
c65e89f6c1
Also enforce privilege checks for SCR reads
Peter Rugg
2020-05-12 13:28:30 +01:00
854151978e
Fix byte-enable merging tag logic in the cache (with help from Alexandre). Also adjust priority in CCall exceptions.
jon
2020-05-12 12:24:15 +01:00
26919154db
Merge branch 'pdr32-wip' into CHERI
Peter Rugg
2020-05-12 00:19:36 +01:00
8f4c6fbcce
Decode CSpecialRW 0 as AUIPCC
Peter Rugg
2020-05-11 23:52:43 +01:00
f0bcd2ccd1
Don't write on CSpecialRW from R0
Peter Rugg
2020-05-11 23:52:04 +01:00
ec9f19dc26
Disable assert since normal instructions can read SCRs
Peter Rugg
2020-05-11 22:39:12 +01:00
20eb1129b1
Complete PCC checks
Peter Rugg
2020-05-11 17:25:21 +01:00
0ee9c65f3a
Forward cap-only instructions to the ALU
Peter Rugg
2020-05-11 17:24:43 +01:00
461ca6a703
Merge branch 'CHERI' into pdr32-wip
Peter Rugg
2020-05-11 14:08:42 +01:00
6e00bd627b
Implement x0 default value in the memory pipe.
jon
2020-05-11 12:21:57 +01:00
cf39ec8368
Move to semantics suggested by Jess where we throw the exception on the type of the code capability (src1, hopefully?) if the type is reserved.
jon
2020-05-11 11:39:10 +01:00
e3b532089d
Bounds-check the target of CCall. Also handle more invalid decodings of explicit capability instructions correctly.
jon
2020-05-08 12:15:35 +01:00
9631a9db4b
Rework exceptions in the memory pipeline to reconverge with the original exception flow. This solves some issues with exceptions not being known in some parts of the pipeline due to bypassing them.
jon
2020-05-07 19:35:00 +01:00
f5ec436d19
Bump cheri-cap-lib
Peter Rugg
2020-05-07 16:34:09 +01:00
27947f4df7
Refactoring around SCRs
Peter Rugg
2020-05-07 16:19:26 +01:00
77c7a6f3c0
Use the existing functions for casting.
jon
2020-05-07 13:20:11 +01:00
e3664c2bfd
Do sign extension properly on loads.
jon
2020-05-07 12:17:14 +01:00
9c0130a200
Support for permissions and bounds checks for memory operations, taking the cap mode into account.
jon
2020-05-06 18:48:44 +01:00
cbb0d859c7
Feed capability checks and bounds checks into the memory pipe and back into the reorder buffer.
jon
2020-05-05 18:28:28 +01:00
500811430b
Initial support for decoding Capability Memory instructions.
jon
2020-05-05 12:23:10 +01:00
21d1207e6b
The beginnings of an implementation of LQ and SQ. Also a bug-fix to unseal nextPCC for control flow instructions, which should only affect CCall (which was leaving PCC sealed).
jon
2020-05-01 17:26:41 +01:00
0177c2cd6e
Use the bounds of PCC to check legacy control flow instructions rather than the bounds of the newPCC after C(Set/Inc)Offset, which may have become unrepresentable.
jon
2020-05-01 12:17:20 +01:00
90d9d7cbc7
Move back to considering the instruction width when checking PCC.
jon
2020-04-30 15:32:26 +01:00
b70498e00a
Try new types to hold capabilities
Alexandre Joannou
2020-03-20 15:41:50 +00:00
0b68498940
Fix interface with special capability register file trap handling. Call the correct trap function, and report the correct privilege level.
jon
2020-04-30 11:59:34 +01:00
6dff23f30a
Added BLUESPECDIR to read me
Marno van der Maas
2020-04-30 11:56:13 +01:00
44199a841b
Only check the bounds of nextPc if the branch is taken...
jon
2020-04-29 18:34:02 +01:00
1439fe98c7
Fix 2 bugs. Restore from sepc on sret. To "inclusive" bounds check on Jumps and Branches.
jon
2020-04-29 13:42:23 +01:00
d3e0908785
Check PCC bounds in rename.
jon
2020-04-28 19:08:07 +01:00
68d4afa8c9
Added submodule update to read me
Marno van der Maas
2020-04-28 14:58:35 +01:00
1cf28c0d1d
Added link to verilator build instructions
Marno van der Maas
2020-04-28 14:41:01 +01:00
ab6b8966db
Bounds-check legacy jalr and br correctly.
jon
2020-04-28 11:47:09 +01:00
f63d55d4e5
Fix bug; consistently treat mepc as the offset of mepcc. Also remove PCC from the SCR file.
jon
2020-04-27 17:36:02 +01:00
e5b7ba6b13
Fixes to build with cap PCC for non RVFI-DII case
Alexandre Joannou
2020-04-27 16:48:34 +01:00
d24750f0ec
Bump the capability library.
jon
2020-04-27 15:56:48 +01:00
jon