Cheri-research/Toooba
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  • f0bfea4590 Bump submodule. Jonathan Woodruff 2020-03-12 12:24:13 +00:00
  • 5851d254ad Add a needed verilog file. Jonathan Woodruff 2020-03-12 11:48:09 +00:00
  • 0d525e4d11 Add RVFI_DII build Makefile. Jonathan Woodruff 2020-03-12 11:18:44 +00:00
  • b24b6ab109 Bump the RVFI_DII library. Jonathan Woodruff 2020-03-12 10:47:30 +00:00
  • 79935d848f Reduce "verbosity". Jonathan Woodruff 2020-03-12 10:47:07 +00:00
  • 41fd6b2b60 Updated conditions to print the destination register and value correctly for various instruction types. Jonathan Woodruff 2020-03-12 10:46:00 +00:00
  • a7a2854888 Declarations required for updated socket library. Jonathan Woodruff 2020-03-12 10:45:34 +00:00
  • f02e9af515 Improved avoidance of initial timer interrupt in MMIOPlatform; removed spurios MSTATUS TV report on CSRRS/C with rs1==0 rsnikhil 2020-03-11 22:42:18 -04:00
  • 3eccf92544 Move to 8 MiB RVFI-DII memory. Jonathan Woodruff 2020-03-11 11:53:19 +00:00
  • a19eb97f34 Small tweak to MMIOPlatform.bsv to avoid spurious timer interrupt at start of time. rsnikhil 2020-03-09 22:58:04 -04:00
  • b00f1d2eec Fixed a Tandem Verification trace generation bug for FMV.X.F and FMV.X.D rsnikhil 2020-03-09 14:47:20 -04:00
  • 976494a8ff Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR. rsnikhil 2020-03-08 21:29:30 -04:00
  • fafd99c983 Fixes reported by Joe Stoy: PLIC, MMIO_AXI4_Adapter and Core.bsv (details below) rsnikhil 2020-03-08 15:39:57 -04:00
  • 0ac138b08f UART_Model.bsv fixes for better support of 32b/64b fabrics and 4-byte/8-byte address strides rsnikhil 2020-03-05 09:33:58 -05:00
  • 4bdbcbfd88 Additional fix to previous commit (75df204e) which only fixed MIP/MIE; this fixes SIP/SIE as well. rsnikhil 2020-03-04 13:14:31 -05:00
  • 75df204e31 Fixed a Tandem-Verification bug (reporting incorrect MIP/MIE/SIP/SIE post-write values) rsnikhil 2020-03-04 09:50:39 -05:00
  • 40b55d2c32 Fixed a Tandem-Verification issue (report MIP change due to interrupts). rsnikhil 2020-03-03 18:34:00 -05:00
  • ac6043ce2d Fixed two bugs: (1) not trapping on unimplemented CSRs (2) MSTATUS.FS initialization rsnikhil 2020-03-03 13:56:31 -05:00
  • e02dac1449 In CsrFile.bsv, changed user-privilege bits in MIP/SIP/MIE/SIE to read-only 0 since MISA.N=0 rsnikhil 2020-03-02 16:20:07 -05:00
  • 96a0897bf5 In MMIO_AXI4_Adapter.bsv, added check for unmapped addresses, provide err response immediately. rsnikhil 2020-02-28 14:07:45 -05:00
  • 6f5d079e7c Modified synth and sim compile options in the Makefile Regenerated synth and sim RTLs Niraj N Sharma 2020-02-22 17:51:13 +05:30
  • 568f52fc0b Corrected typo in src_SSITH_P3 Makefile Niraj Sharma 2020-02-14 21:51:17 -05:00
  • 0264984136 Numerous fixes, so now generating correct Tandem-Verification traces for all 229 ISA tests. rsnikhil 2020-02-14 15:37:20 -05:00
  • 8434df2dac Fixes for Tandem Verification for store-values, CSR values on traps, etc. (detail below) rsnikhil 2020-02-12 19:43:04 -05:00
  • ddcb784297 Bugfix: TV_Encode, after NDM_RESET, was not back to a neutral starting point. rsnikhil 2020-02-12 10:44:30 -05:00
  • a99f046cdc Regenerated RTL in src_SSITH_P3 with TANDEM_VERIF Niraj Sharma 2020-02-12 09:24:33 +05:30
  • 30f124db7d Updated Tests/isa/ contents from newer versions in Flute rsnikhil 2020-02-11 20:45:03 -05:00
  • c8fde208e9 Fixed typo in TV_Encode.bsv; now successfully running with both GDB and Tandem Verif rsnikhil 2020-02-11 19:55:26 -05:00
  • 82e56c2908 Fixed Tandem Verif trace gen for CSRRx on WARL regs: report post-WARL-xformed write-data rsnikhil 2020-02-11 15:46:24 -05:00
  • db114186af More progress towards Tandem Verification trace generation (detail below) rsnikhil 2020-02-10 15:08:08 -05:00
  • 08db480be3 Merge branch 'master' of https://github.com/bluespec/Toooba rsnikhil 2020-02-07 23:13:35 -05:00
  • c0ae2776e8 Further additions to Tandem Verification trace info. rsnikhil 2020-02-07 23:10:53 -05:00
  • e35c48efff Merged src_SSITH_P3 and src_SSITH_P3_sim Niraj Sharma 2020-02-07 21:00:16 +05:30
  • af0b1ef415 Incremental additions to Tandem Verification trace gen rsnikhil 2020-02-06 20:46:26 -05:00
  • c14c9b3e6c Minor tweaks, mostly cosmetic and $displays rsnikhil 2020-02-06 14:15:56 -05:00
  • 8e0f0afb85 Reflected reset related changes from src_SSITH_P3 to src_SSITH_P3_sim Niraj Sharma 2020-02-06 17:19:17 +05:30
  • e02b352bbb Resetting tv_encode whenever the proc is started Niraj Sharma 2020-02-06 17:17:28 +05:30
  • 454b83fe9a Added corew.start calls after NDM reset and PoR Niraj Sharma 2020-02-06 17:16:34 +05:30
  • d8a3c3d754 Generated src_SSITH_P3_sim RTL Niraj Sharma 2020-02-06 17:14:59 +05:30
  • 83829590dd Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module rsnikhil 2020-02-04 16:02:53 -05:00
  • 4960a59da0 Fixes for GDB control: can run consecutive tests in single simulation, without intermediate reset. rsnikhil 2020-01-30 22:46:51 -05:00
  • d8ca3c897b Merge pull request #10 from nirajnsharma/master Rishiyur S. Nikhil 2020-01-30 19:13:33 -08:00
  • ce327a1615 Updated SoC_Map in src_SSITH_P3 (synth version) Regenerated synth RTL Niraj Sharma 2020-01-30 14:04:29 -05:00
  • a0a4093088 Set verbosity to 0 in TV_Encode and Trace_Data2_to_Trace_Data Updated src_SSITH_P3_sim SoC_Map Niraj N Sharma 2020-01-30 13:39:54 -05:00
  • f89ed020d8 Added src_SSITH_P3_sim directory Niraj N Sharma 2020-01-30 20:16:08 +05:30
  • 6078b7ce19 Removed EXTERNAL_DEBUG_MODULE stuff from CoreW.bsv; added Tandem Verif control flow rsnikhil 2020-01-29 13:19:31 -05:00
  • d84ec657d7 Fixed SSITH_P3 version of SoC_Map; regenerated SSITH_P3 RTL rsnikhil 2020-01-28 21:33:56 -05:00
  • 154ed3d47f Fixed LLCDmaConnect to allow 1,2,4,8-byte accesses from Debug Module rsnikhil 2020-01-28 20:57:39 -05:00
  • 4a7dd01023 Removed -D EXTERNAL_DEBUG_MODULE in src_SSITH_P3 Makefile, and added an undef in src_Core/Core/CoreW.bsv rsnikhil 2020-01-23 12:25:21 -05:00
  • fa5e141550 Fixed resume-after-break problem (details below). rsnikhil 2020-01-17 20:08:04 -05:00
  • 977e3c92cd Fixed some ifdef INCLUDE_GDB_CONTROL issues. Passing all 229 ISA tests. rsnikhil 2020-01-16 16:04:32 -05:00
  • 4b2400fcc9 Merge remote-tracking branch 'origin/Debug_Module' rsnikhil 2020-01-16 14:41:22 -05:00
  • 56698d469e Integration of Debug_Module basically complete (except resume-after-break, details follow) rsnikhil 2020-01-16 14:36:19 -05:00
  • 16cb92e2c1 Register reads now working. All functionality is in; need testing, cleanup, merge into master. rsnikhil 2020-01-15 15:54:50 -05:00
  • 2e909a90a9 Work-in-progress integrating Debug Module. Now able to load ELF file from debugger and execute it rsnikhil 2020-01-14 23:29:32 -05:00
  • 2807edf1b2 Work-in-progress on integrating Debug Module rsnikhil 2020-01-13 21:22:54 -05:00
  • dcfb285c29 Work-in-progress. Now able to single-step from debugger. rsnikhil 2020-01-13 15:34:27 -05:00
  • fd9786cc71 Merge pull request #8 from nirajnsharma/master Rishiyur S. Nikhil 2020-01-13 09:25:43 -08:00
  • 64178e0bd7 Updated src_SSITH_P3 RTL for simulation Niraj N Sharma 2020-01-13 12:19:20 -05:00
  • 27c3c7cb4d Work in progress on Debug Module integration. Got further on start/step/halt rsnikhil 2020-01-12 22:25:14 -05:00
  • 1278927f51 Removed a block-commented piece of code rsnikhil 2020-01-08 20:31:33 -05:00
  • cd779e1cbe Work in progress: updates to handle stop/step/run from Debug Module rsnikhil 2020-01-08 20:17:50 -05:00
  • 0f04b9cbe1 Tweaks to builds/Resources/Include_..._.mk rsnikhil 2020-01-08 19:49:49 -05:00
  • 09340dac13 Merge pull request #7 from jrtc27/bluesim Rishiyur S. Nikhil 2020-01-04 14:54:43 -08:00
  • 7ecde58b1d Add RV64ACDFIMSU_Toooba_bluesim build James Clarke 2020-01-04 22:38:28 +00:00
  • 7b6c1e655b Avoid divide-by-zero in simulation model James Clarke 2020-01-04 05:12:16 +00:00
  • 6927e6bab1 Add simulation model for ResetGuard James Clarke 2020-01-04 04:35:31 +00:00
  • f101ad129e Full RVFI flow-control integration with Toooba's flow control. This enables us to run all test classes successfully. Jonathan Woodruff 2019-12-18 15:49:42 +00:00
  • 909423e8e8 Use smaller L2 size (256KiB) for TestRIG. Jonathan Woodruff 2019-12-13 13:00:52 +00:00
  • 584f8334fa Pipe through memory results. This design passes 100 memory test sequences of TestRIG. Yay! Jonathan Woodruff 2019-12-13 10:53:02 +00:00
  • 82ba66b15e Changes to support vectored RVFI_DII bridge directly, which enables us to successfully run memory tests with traps. Jonathan Woodruff 2019-12-09 16:34:27 +00:00
  • b79a11b44d Merge branch 'master' into RVFI_DII Jonathan Woodruff 2019-12-09 16:33:51 +00:00
  • 83e54f9b53 Changes necessary to trace memory operations. This is not thoroughly tested, as we quickly throw an exception due to out-of-bounds memory and need some RVFI-DII control flow fixup to proceed further. Jonathan Woodruff 2019-11-29 10:50:38 +00:00
  • 96d092c300 Changes that enable RVFI_DII to run. It doesn't yet pass any set of tests, but tests do run and reduce. Jonathan Woodruff 2019-11-26 10:46:56 +00:00
  • 571904535e Add RVFI_DII BSV interface subrepo. Jonathan Woodruff 2019-11-07 16:11:54 +00:00
  • d337f1b8cf Update compiled output. Darius Rad 2019-10-25 00:13:58 -04:00
  • 35e0b09202 Merge pull request #6 from nirajnsharma/master Rishiyur S. Nikhil 2020-01-03 04:37:48 -08:00
  • 364b1d1cf3 For src_SSITH_P3 builds, added conditions to include/exclude simulation models of the integer divider Niraj Nayan Sharma 2020-01-03 16:59:34 +05:30
  • afce8b4a6d Merge pull request #5 from jrtc27/fixes Rishiyur S. Nikhil 2020-01-01 17:26:32 -08:00
  • 9ff062a5db Fix FMIN/FMAX ISA test failures James Clarke 2020-01-02 01:12:51 +00:00
  • 8a2c45c901 Merge pull request #4 from jrtc27/fixes Rishiyur S. Nikhil 2020-01-01 16:28:44 -08:00
  • 60c1e31b01 Reduce needless fetch stalls in presence of compressed instructions James Clarke 2020-01-01 22:22:17 +00:00
  • 5df163d414 Merge pull request #3 from nirajnsharma/master Rishiyur S. Nikhil 2019-12-24 07:51:17 -08:00
  • 601bbe5a82 No longer using Xilinx FPU modules Niraj Nayan Sharma 2019-12-14 12:44:02 +05:30
  • 09ce172b91 FP ISA tests bug fixes: Added nanboxing for float in a 64-bit FPR system Fixed behaviour around NaNs for comparison opcodes Niraj Nayan Sharma 2019-12-06 14:27:33 +05:30
  • 021b374833 Merge pull request #2 from jrtc27/fixes Rishiyur S. Nikhil 2019-11-26 12:15:22 -05:00
  • 3b5443e284 FetchStage: Clear straddle state on redirect James Clarke 2019-11-03 04:59:52 +00:00
  • 67be950d3a FetchStage: Use EHRs to remove conflicts between doDecode and doFetch3 James Clarke 2019-11-03 04:12:34 +00:00
  • 87daa8e319 Revert unwanted MMIOInst diff in e7fbf32b38 James Clarke 2019-11-03 03:47:25 +00:00
  • 78cad5bbcc Fix BTB entry aliasing with C extension James Clarke 2019-11-02 20:38:35 +00:00
  • a0fd5a8f37 Print cycle counter like Piccolo/Flute on write to to_host James Clarke 2019-11-02 20:37:34 +00:00
  • bb557e5e23 Update compiled output. Darius Rad 2019-04-24 21:48:33 -04:00
  • 4fba332f17 Add missing module (FIFOL1) to Xilinx import. Darius Rad 2019-04-22 22:04:20 -04:00
  • 532998461d Merge branch 'master' of https://github.com/bluespec/Toooba rsnikhil 2019-04-22 15:12:52 -04:00
  • 666dd2ad92 Small tweak to remove unnecessary explicit boot rom addrs (subsumed by IO) rsnikhil 2019-04-22 15:12:30 -04:00
  • afb5e0d13c Update compiled output. Darius Rad 2019-04-22 13:55:36 -04:00
  • 4a8fcef186 Start processor after reset. Darius Rad 2019-04-10 13:38:04 -04:00
  • 51bdff05d8 Updated Run_regression.py to utilize parallel processes rsnikhil 2019-04-18 18:42:06 -04:00
  • fd02260fc8 Merge branch 'master' of https://github.com/bluespec/Toooba rsnikhil 2019-04-17 18:09:20 -04:00
  • e7fbf32b38 Bugfix in MMIOPlatform.bsv for instruction-fetch from IO addrs rsnikhil 2019-04-17 15:29:10 -04:00