1ef2d0cbeb
Include both execute redirect and commit redirect in "redirect" counter.
jon
2021-03-09 15:57:15 +00:00
da1fd3781a
Correction in testbench section
Marno van der Maas
2021-03-09 10:58:56 +00:00
f3f52d85ea
Added links to RiscyOO and CHERI
Marno van der Maas
2021-03-09 10:55:17 +00:00
d3f40216a9
Made the unimplemented notation consistent
Marno van der Maas
2021-03-09 10:46:55 +00:00
fe7977e4e9
Fix typo when removing commented out code.
jon
2021-03-06 07:24:49 +00:00
8da520175f
Use an (unguarded) BRAM in the Btb. Also, assume that a target that is not taken should be removed from the Btb. (The read that checked isn't possible with BRAM timing unless we latched and had an extra port, but removing the check actually improved performance a bit in CoreMark, and the pipeline should actually only be reporting a non-taken branch if we did something wrong.)
jon
2021-03-06 07:19:50 +00:00
4b411bf752
A Btb with 1/4 the storage that will (hopefully) infer as BRAM.
jon
2021-03-05 12:14:26 +00:00
7aea0325fc
Add cycles to commit instruction reports to help with performance debugging.
jon
2021-03-05 12:12:33 +00:00
89f0c3a45f
Reduce verbosity.
jon
2021-03-05 12:11:49 +00:00
39e895ca4e
added documentation of hardware performance monitoring events
Franz Fuchs
2021-03-04 16:45:02 +01:00
6ea387f744
Fix performance bug in PC compression where we execute across a page boundary.
jon
2021-03-04 14:40:57 +00:00
0e1e2249a6
Default to dual-core builds
Peter Rugg
2021-03-04 11:54:32 +00:00
db08e96596
Add Btb to the component.xml.
Jonathan Woodruff
2021-03-03 20:27:31 +00:00
7a1d234e40
Merge branch 'ifetch-cleanup' into CHERI
Peter Rugg
2021-03-02 11:57:31 +00:00
9dc27542f3
Use order-only prerequisites for directories
Jessica Clarke
2021-02-28 04:14:54 +00:00
e1060ac43d
TlbTypes: Fix exception code reported for some store page fault conditions
Jessica Clarke
2021-02-28 03:51:05 +00:00
5b6e8d88f6
Add CSetEqualExact
Peter Rugg
2021-02-22 17:44:36 +00:00
53eb073fb2
Don't track generated Verilog
Peter Rugg
2021-02-19 19:43:28 +00:00
2f0b0c110f
Use the necessary number of ports.
jon
2021-02-19 17:37:17 +00:00
b5bce1209a
Revert "Revert biggest scheduling change from potentially problematic commit." This one does not actually build with the new BSC compiler. I forgot to test the hardware build (with GDB), which is where we have the problem. This reverts commit b4308e9a6e.
jon
2021-02-19 17:15:53 +00:00
9f0968b1cb
Fix AXI_Size=16 for MMIO of caps
Peter Rugg
2021-02-19 17:19:47 +00:00
47c94b5a34
Map more RAM in SSITH build
Peter Rugg
2021-02-19 09:24:46 +00:00
b4308e9a6e
Revert biggest scheduling change from potentially problematic commit. This still builds with the new BSC compile.
jon
2021-02-18 15:18:58 +00:00
1fbf786294
Add to synthesis file set.
jon
2021-02-17 21:26:54 +00:00
eaf7a4ace7
Add one more missing file and clean up some duplicates.
jon
2021-02-17 18:37:52 +00:00
0f3fd15d41
Initial implementation of map of HPM counters into supervisor and user mode. This version just unconditionally exposes them.
jon
2021-02-17 17:07:53 +00:00
5ba685b541
Try harder to remove all copies of references to old files.
jon
2021-02-17 16:57:01 +00:00
7a59cad288
Remove more no-longer-generated files from component.xml
jon
2021-02-17 15:54:27 +00:00
9d2acbd96d
Bump to latest version of Bluestuff.
jon
2021-02-17 14:59:31 +00:00
059f189bba
Attempt to add all current source files to componenet.xml.
jon
2021-02-17 14:35:49 +00:00
4c19a34eda
Workaround for scheduling issues when using PERFORMANCE_MONITORING (with jdw57)
Alexandre Joannou
2021-02-15 18:07:08 +00:00
e3b776a81f
Clarified supported versions of verilator
Marno van der Maas
2021-02-12 09:49:17 +00:00
9e36ff95cd
Roll back accidental commit of experimental change.
jon
2021-02-11 12:22:00 +00:00
96be5802a0
Bump BlueStuff with workaround.
jon
2021-02-10 17:23:46 +00:00
40ea082310
Some updates to build with the new bsc compiler.
jon
2021-02-10 17:21:35 +00:00
9dd2dd9c77
Bump cheri-cap-lib.
jon
2021-02-09 19:20:47 +00:00
65d0edd722
Bump BlueStuff to fix compiler error with new bsc
Marno
2021-02-10 14:07:02 +00:00
a78d09c522
Add ifdefs for GDB control on helper functions
Peter Rugg
2021-02-08 14:48:54 +00:00
fb5339e9ca
Adapt the PLIC instantiation and wiring to support multiple cores
Jessica Clarke
2020-10-16 16:14:24 +01:00
cedb4c279d
Ensure the MMIO platform issues aligned requests by changing the AXI4_Size field based on the byte enables
Peter Rugg
2021-01-31 17:34:35 +00:00
44e19afbf3
Fix MMIO bug missing uncached instruction bytes with certain alignments
Peter Rugg
2021-01-30 15:22:22 +00:00
f800cdeb77
Prevent spurious warnings
Peter Rugg
2021-01-30 15:21:38 +00:00
d340066f6f
Multicore debug cleanups
Peter Rugg
2021-01-21 20:51:02 +00:00
30e7090213
Multicore debug-module
Peter Rugg
2021-01-21 20:25:26 +00:00
3417fb454e
Revert "Provide opt-in wedge debugging info" - some missed changes
Peter Rugg
2021-01-19 22:00:16 +00:00
20f1ddf587
Revert "Plumb through a lot more ROB debug state"
Peter Rugg
2021-01-19 21:40:59 +00:00
a6ab823d1d
Revert "Cover interesting fetch and rename state for DEBUG_WEDGE configs"
Peter Rugg
2021-01-19 21:39:59 +00:00
c515fb4518
Remove commented-out code.
jon
2021-01-08 12:20:53 +00:00
a6771219ba
Fold the fragment count into the standard pipeline structs.
jon
2021-01-08 11:57:46 +00:00
fc968c867f
PC compression scheme for the instruction fetch pipeline. Store the upper bits of the PC in a table and only handle indices and lsbs in the main pipeline. This eliminates redundancy between PCs and predicted PCs, and even more between fragments of instructions.
jon
2021-01-07 17:56:45 +00:00
dd82b2703c
Record an exception from either half of an instruction, with preference for the first half.
jon
2020-08-19 16:05:01 +01:00
0d93ed3ad2
Merge branch 'CHERI' into ifetch-cleanup
jon
2021-01-13 15:21:20 +00:00
e3f94224de
Revert "Cause two surprising conditions to not throw slave errors as this is not"
Jessica Clarke
2020-12-21 13:03:13 +00:00
92ca72a6e2
Fix build error by providing default.
Jonathan Woodruff
2020-12-18 17:55:18 +00:00
84d60d03b1
Merge pull request #6 from nwf/capdirty
Jonathan Woodruff
2020-12-18 16:48:56 +00:00
f86d4d9dc0
Add counter support to ITLB.
jon
2020-12-17 17:57:43 +00:00
4ddcaff497
Support for data TLB counters.
jon
2020-12-17 16:52:45 +00:00
4dd0a73051
Port to internal AXI interfaces for the debug module.
Jonathan Woodruff
2020-12-17 15:02:05 +00:00
bab989d6d2
Support for stat counters from the tag controller. The order of the events is very not tested; 50% chance of being correct.
jon
2020-12-17 12:38:52 +00:00
4131dcd073
Cause two surprising conditions to not throw slave errors as this is not specified and causes kernel panics. Hopefully the details of what should happen in these cases is correct, but we shall see...
jon
2020-12-17 12:37:45 +00:00
fa9931b64c
Implement a couple Cache counters in the LLCache. These aren't too useful... We don't seem to have normal counters for loads and stores in the baseline.
jon
2020-12-15 18:16:21 +00:00
17a7a32092
Use DRegOR instead of immitating latching behaviour.
jon
2020-12-15 16:18:36 +00:00
d64df09d82
Bump to version with DRegOR.
jon
2020-12-15 16:18:18 +00:00
b6a397df52
Support for ICache stat counters.
jon
2020-12-15 14:49:16 +00:00
73d25bf8f5
Support performance counters (hopefully) in the caches. The DCache should be fully wired up.
jon
2020-12-14 18:10:06 +00:00
982758cae7
Bump to version of Bluestuff that has the saturating truncate function.
jon
2020-12-14 12:13:34 +00:00
f6569e2d14
Actually do the intended fix, not just inverting the variable
Jessica Clarke
2020-12-14 10:51:57 +00:00
295b878836
Fix negated CYCLE/INSTRET logic for ASR and make less confusing
Jessica Clarke
2020-12-14 10:50:23 +00:00
6768bf92c7
iMove the store count to the pipeline write. It appeared to be counting capabilities in store counter flushes, which, FI think, is not quite what was intended in this counter.
jon
2020-12-11 17:16:38 +00:00
19a07882ab
CSome style cleanups from chat with Alexandre.
jon
2020-12-11 16:44:59 +00:00
1bae03da9c
Implement all the remaining core (not cache) memory stat counters.
jon
2020-12-11 15:47:04 +00:00
d6243be1dd
Add a few more core performance counters.
jon
2020-12-04 18:34:56 +00:00
bdc2d494f2
Change name something that makes sense.
jon
2020-12-04 17:12:26 +00:00
3f60c046f7
Fix typo.
jon
2020-12-04 16:51:44 +00:00
f42c3f3577
Merge branch 'cheri-perfmon' into CHERI
jon
2020-12-04 16:29:51 +00:00
5665d2e9cd
A more effective Fence count (as some fences go through as the Nop iType).
jon
2020-12-04 16:28:19 +00:00
425c2778c0
Bump Bluestuff to get resetting in the Performance Monitor.
jon
2020-12-03 17:55:03 +00:00
1fb388fb18
Count more things correctly.
jon
2020-12-03 17:54:46 +00:00
8a13b866d7
Bump bluestuff to the one with generalised report width.
jon
2020-12-02 15:31:49 +00:00
4fcc18635a
Supporting most architectural counters, wiring them out from CommitStage. Also support multiple events per cycle.
jon
2020-12-02 15:28:41 +00:00
e99e1e6274
Update CSR names to fullish standard names.
jon
2020-12-02 10:18:25 +00:00
742c4c5c92
Bump Bluestuff.
jon
2020-12-01 18:03:44 +00:00
259d34618c
A design that actually passes one performance monitor trace from TestRig. The example counted redirections, which happend to match between Flute and Toooba for this example.
jon
2020-12-01 18:02:11 +00:00
98a9c076cd
Update BlueStuff API and Bump BlueStuff and TagController
Alexandre Joannou
2020-12-01 00:33:48 +00:00
0289bfe17d
Fix a couple errors due to changes somehow merged over from the rich_predicted_state branch.
Jonathan Woodruff
2020-11-09 11:14:11 +00:00
jon