Cheri-research/Toooba
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  • 328592b068 Added missing slash in readme Marno van der Maas 2020-10-29 15:45:17 +00:00
  • 29168574ca Revert "Sort of support 2 cores for starting and halting." Jonathan Woodruff 2020-10-16 15:44:53 +01:00
  • b4b7718aa2 Sort of support 2 cores for starting and halting. jon 2020-10-08 15:00:43 +01:00
  • 844bfd5e79 Merge pull request #5 from nwf/capdirty PeterRugg 2020-10-02 17:17:24 +01:00
  • ed9541e8d0 Put all dirs for source description in code blocks Marno van der Maas 2020-10-02 13:09:51 +01:00
  • d4308f0f03 Slightly rework CHERI PTE to add CapDirty flag Nathaniel Filardo 2020-09-30 15:40:50 +01:00
  • 9508eada79 Change to allow 1-way superscalar to build without error. jon 2020-09-17 14:40:46 +01:00
  • 1568fcf485 Enable larger than 2x superscalar by using explicit ports into the BTB. (Previously we ran into the limit of ports on the regFiles holding state in the BTB. This uses a vector of regFiles with a vector of interfaces, which is logically the same but might produce multiple copies of state.) jon 2020-09-16 11:42:19 +01:00
  • 96afb0a7f5 FIFO optimisation both for build time (and possibly condition complexity?) and for throughput. jon 2020-08-13 17:33:46 +01:00
  • 4c74d27e4e Merge branch 'CHERI' into ifetch-cleanup jon 2020-08-11 15:31:30 +01:00
  • 7a93056b8b Increase the capacity of f32d to enable full throughput. I don't know why this is necessary, but this allows performance parity with the baseline. jon 2020-08-11 15:30:03 +01:00
  • 9230fcc3b4 Merge branch 'CHERI' into ifetch-cleanup jon 2020-08-11 15:25:12 +01:00
  • 00ffdd7228 Enable to build with latest BSC compiler. jon 2020-08-11 14:46:28 +01:00
  • 3b97fbe255 Rename last->prev for clarity. jon 2020-07-31 13:46:33 +01:00
  • f63673c3f3 First working implementation of the new instruction picker. Evidence of "working" is passing TestRIG to a cursory depth including compressed instructions and running CoreMark in simulation. This one appears to be 2.5% slower than the existing design in CoreMark, so some optimisation should be done. We expect it to be a bit faster than the original due to more flexibility in decoding instructions from different fetch units together. jon 2020-07-31 11:25:28 +01:00
  • 3a9e76c1fd Fix bug where the wrong bounds were attached to a mispredicted half of an instruction. jon 2020-07-29 12:32:28 +01:00
  • 8896bb27f1 Revert "Remove the special flush from the Fetch3 stage." jon 2020-07-29 11:40:00 +01:00
  • 4fe24c9cd5 Remove the special flush from the Fetch3 stage. This is an intermediate simplification for moving to SupFifo-based picking. jon 2020-07-29 07:38:35 +01:00
  • 3132f9f55f Trap when writing PCC, rather than silently ignoring Peter Rugg 2020-07-28 12:57:13 +01:00
  • 73dedec309 FetchStage: Use map rather than for loop Jessica Clarke 2020-07-24 20:02:10 +01:00
  • 0b3ad23c24 Fix typo Jessica Clarke 2020-07-24 19:10:11 +01:00
  • 1bad5b080b Various updates to README.md Jessica Clarke 2020-07-24 19:06:56 +01:00
  • 44d49a52c0 Drop removed CHERI directory from README.md (Closes: #3) Jessica Clarke 2020-07-24 18:47:26 +01:00
  • 40af067a71 Fix RVFI_DII build in the presence of 2-byte bundles. jon 2020-07-24 17:28:46 +01:00
  • 1f968b0c07 2-byte aligned instruction memory to simplify compressed instruction fetch. jon 2020-07-24 12:38:37 +01:00
  • ecce475b97 Merge branch 'mem_perm_checks' into CHERI Peter Rugg 2020-07-23 16:53:14 +01:00
  • 27082ee2a9 Report writes to PCC as illegal instruction, not ASR violation Peter Rugg 2020-07-23 15:40:28 +01:00
  • 97d89086a6 Bump cheri-cap-lib Peter Rugg 2020-07-23 11:20:30 +01:00
  • e8aa873c2e Prevent 'insufficient type info' warning Peter Rugg 2020-07-23 11:18:31 +01:00
  • a6b40e946b Prevent using CCSeal to 'seal over' other types Peter Rugg 2020-07-23 11:18:07 +01:00
  • c693462f6b Add tag-clearing due to cap load perm and PTE bits Peter Rugg 2020-07-22 15:54:49 +01:00
  • 0040b05ada Add page table cap store checking Peter Rugg 2020-07-21 16:02:37 +01:00
  • 2f4f5ca838 FetchStage: Reduce diff to upstream Jessica Clarke 2020-07-21 13:24:54 +01:00
  • 0516db5e8d Bump BSV-RVFI-DII and refactor to support new parcel-based interface Jessica Clarke 2020-07-21 13:24:39 +01:00
  • 7d98946103 Working compressed instruction support. jon 2020-07-20 19:49:52 +01:00
  • d7a4d3497b Keep unaligned instruction fetch from breaking DII. jon 2020-07-17 16:39:13 +01:00
  • 4d2f971767 Assign the correct PC to fetched instructions. jon 2020-07-17 11:07:19 +01:00
  • 72f49a1109 Regenerate verilog Jessica Clarke 2020-07-16 19:35:51 +01:00
  • 2b8e5f1dad FetchStage: Inline unnecessary local variable Jessica Clarke 2020-07-16 18:13:43 +01:00
  • a74596c956 Fix CCall being impossible Peter Rugg 2020-07-16 14:06:26 +01:00
  • 5efd7d5cd8 Partially bring back tval Jessica Clarke 2020-07-15 04:24:02 +01:00
  • 682ff10d72 Regenerate verilog Jessica Clarke 2020-07-15 02:58:29 +01:00
  • 7eff218288 Replace enums-for-constants with structs wrapping a plain Bit#(n) Jessica Clarke 2020-07-15 02:43:50 +01:00
  • b65576b112 Copy TAP file generation code from Flute Jessica Clarke 2020-07-15 03:10:15 +01:00
  • b44a912756 Don't require ASR to read PCC Peter Rugg 2020-07-14 22:41:51 +01:00
  • e8c1de7793 Regenerate verilog Jessica Clarke 2020-07-14 19:01:47 +01:00
  • 956c9686a6 src_SSITH_P3: Optimise unspecified values Jessica Clarke 2020-07-14 17:53:01 +01:00
  • 6356d5f8a1 Drop check against whether the ROB row already has a trap Jessica Clarke 2020-07-14 16:46:29 +01:00
  • f2d9c78824 Drop unused exception parameter on FPU ROB ports Jessica Clarke 2020-07-14 16:37:59 +01:00
  • 0b7d635cbf Drop unused store_data/store_data_BE arguments when TV is disabled Jessica Clarke 2020-07-14 14:21:51 +01:00
  • 5a42b0102a Turn pc back into a Reg Jessica Clarke 2020-07-14 14:15:54 +01:00
  • 9bdf71ee4e Only store the actual address for completed loads/stores Jessica Clarke 2020-07-14 14:11:10 +01:00
  • 675caad0ac Trap for permission failures on mem access Peter Rugg 2020-07-14 15:34:38 +01:00
  • e89f7a8130 Regenerate verilog Jessica Clarke 2020-07-13 18:54:53 +01:00
  • 26a5376f9c FetchStage: Tidy up comment that no longer applies Jessica Clarke 2020-07-13 18:23:01 +01:00
  • 83b734ed87 Remove commented-out code. jon 2020-07-13 18:20:56 +01:00
  • f638644b84 Remove tval from the reorder buffer and just use PC. It's currently unknown to me what the function of tval in the reorder buffer was, which is a bit scary. It seemed to have some additional calculation to do with instruction alignment, but verification with compressed instructions still seems to work. jon 2020-07-13 18:11:13 +01:00
  • 6d4b00c865 Don't push capabilities into FpuMulDivExePipeline Jessica Clarke 2020-07-13 15:52:27 +01:00
  • 4792581d8c Move mux out of Reorder buffer rows into Alu Pipelines. jon 2020-07-13 12:10:41 +01:00
  • eeb6c91b9d Don't use -D_GLIBCXX_USE_CXX11_ABI=0 for bluesim builds Jessica Clarke 2020-07-12 21:32:29 +01:00
  • c66d0183b5 Fix missing serv_socket_init at run time for bluesim RVFI-DII build Jessica Clarke 2020-07-12 21:28:46 +01:00
  • ece8423119 Regenerate verilog Jessica Clarke 2020-07-11 17:26:00 +01:00
  • 98e95b1297 Bump cheri-cap-lib. jon 2020-07-10 20:48:59 +01:00
  • c85ab736d0 Share paths and registers between CSR reads and Special capability registers. jon 2020-07-10 18:41:29 +01:00
  • 6a317d1a00 Prevent instruction fetch to unexpected devices Peter Rugg 2020-07-10 17:34:58 +01:00
  • 5e9b478371 Cover interesting fetch and rename state for DEBUG_WEDGE configs Jessica Clarke 2020-07-10 10:25:53 +01:00
  • 0f65994955 Plumb through a lot more ROB debug state Jessica Clarke 2020-07-09 03:07:07 +01:00
  • 627c60b4e3 Don't generate .depends.mk if bluespec doesn't parse Peter Rugg 2020-07-09 15:20:47 +01:00
  • a0c5d5a9af Roll back changes to SpecPoisonFifo which were accidentally committed. jon 2020-07-09 15:19:39 +01:00
  • 59eddfbb4c Move register in reorder buffer that is only used for Tandem Verification to that case only. jon 2020-07-09 10:26:08 +01:00
  • 40b44d51e2 Merge branch 'CHERI' of https://github.com/CTSRD-CHERI/Toooba into CHERI jon 2020-07-08 12:45:43 +01:00
  • 0b8a031184 Checkpoint FIFO scheduler work. jon 2020-07-08 12:39:13 +01:00
  • 68d3bd484e Provide opt-in wedge debugging info Jessica Clarke 2020-07-07 23:59:35 +01:00
  • 40f8109263 Regenerate verilog Jessica Clarke 2020-07-06 19:32:56 +01:00
  • e9d212fcbc LLC_AXI4_Adapter.bsv: Make more obviously correct Jessica Clarke 2020-07-06 19:01:56 +01:00
  • c406d357c9 Add CHERI+RVFI_DII grant codes and copyrights Peter Rugg 2020-07-06 17:32:21 +01:00
  • a154207d3f CreditCounter.bsv: Actually rate-limit Jessica Clarke 2020-05-15 19:51:43 +01:00
  • 9c12b97a09 Regenerate verilog Jessica Clarke 2020-07-06 01:55:30 +01:00
  • 190e84dfd1 .gitignore. Ignore .depends.mk files Jessica Clarke 2020-07-06 01:55:12 +01:00
  • 17ed2dfde8 Revert CACHE_SIZE back to LARGE Jessica Clarke 2020-07-05 21:44:17 +01:00
  • 7b1259b41b Add a Bluesim RVFI-DII config Jessica Clarke 2020-07-05 21:43:21 +01:00
  • badf5c8e37 Include xCHERI in ARCH and build directory names Jessica Clarke 2020-07-05 21:41:28 +01:00
  • 46ae8ea159 Port parallel build support to bluesim Jessica Clarke 2020-07-05 21:31:44 +01:00
  • 106f70e42b Fix Bluesim build (synced from Verilator Makefile) Jessica Clarke 2020-07-05 21:28:19 +01:00
  • 027b769904 Reduce diff to upstream Jessica Clarke 2020-07-05 21:28:12 +01:00
  • 0b0b863baa Replace home-grown dependency script with Bluespec-provided makedepend.tcl Jessica Clarke 2020-07-05 21:26:18 +01:00
  • cd8e2a15ef Regenerate verilog Jessica Clarke 2020-07-02 03:00:55 +01:00
  • 1173cbb2c6 CsrFile.bsv: Actually respect CHERI fault delegation Jessica Clarke 2020-07-02 02:44:09 +01:00
  • dcc506a365 Regenerate verilog Peter Rugg 2020-07-01 17:08:08 +01:00
  • 20e940eb66 Allow delegation of CHERI traps Peter Rugg 2020-07-01 16:07:08 +01:00
  • 9a00bde2b7 Revert accidentally making simulation memory uncached Peter Rugg 2020-06-30 11:33:43 +01:00
  • f8972768a2 Regenerate verilog Peter Rugg 2020-06-30 00:00:29 +01:00
  • c8e4a64128 Add sentries Peter Rugg 2020-06-29 23:29:08 +01:00
  • 70185dabac Allow debug access to SCR offsets Peter Rugg 2020-06-29 23:27:23 +01:00
  • e403240818 Undo gratuitous whitespace changes. jon 2020-06-26 11:25:46 +01:00
  • 004d039bd8 Reset the UART properly. Also move to non-synth interface for UART. Also annoying whistespace changes to normalise tabs. jon 2020-06-25 18:03:17 +01:00
  • 258a0921e6 Regenerate verilog Peter Rugg 2020-06-25 16:23:40 +01:00
  • 49e384ab2e Don't wedge when peripherals return write errors. jon 2020-06-25 14:58:51 +01:00
  • af6e562c84 Deq the incoming request when sending a fast error response to a bad mapping. jon 2020-06-25 14:19:22 +01:00
  • a5578a715a Regenerate verilog Peter Rugg 2020-06-24 21:16:57 +01:00