Cheri-research/Toooba
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  • 3fd8f22f66 Fix many illegal instruction decode cases Peter Rugg 2025-01-14 16:13:56 +00:00
  • 0ae1d8a275 Clear compressed and uncompressed BTBs on mispred Peter Rugg 2025-01-16 14:54:21 +00:00
  • ce2ded19ae Optimise timing/scheduling by always returning the head of the RAS stack. This means that two returns decoded in the same cycle are likely to result in a misprediction. The trouble here was that the Decode loop wouldn't build with slight changes due to a scheduling conflict through the RAS due to the dependence of the next ras.first method on the earlier ras.pop method. This was indeed an unpleasant combinational path between concurrently decoding instructions. This change allows all RAS predictions to be independent (by assuming no pushes or pops occur earlier in the bundle than a return). Jonathan Woodruff 2025-01-20 15:15:14 +00:00
  • 1ae93da4f8 Restore per-instruction commit prints by default Peter Rugg 2025-01-08 18:43:21 +00:00
  • 1df304a820 Prevent various debug prints by default Peter Rugg 2025-01-08 18:43:05 +00:00
  • d1bea2faf0 Corrected CCSeal decoding function Franz Fuchs 2024-12-20 10:59:15 +00:00
  • 995b978e59 Merge pull request #29 from CTSRD-CHERI/faf28_fix_rvfi_offset Franz Fuchs 2024-12-16 12:19:26 +00:00
  • 2983835e26 Fixed pc_wdata to be addresses instead of offsets Franz Fuchs 2024-12-16 12:13:59 +00:00
  • cf73e1a927 Bump BlueStuff Alexandre Joannou 2024-11-21 18:08:33 +00:00
  • c59520e894 bump BlueStuff gameboo 2024-11-14 14:44:18 +00:00
  • 817d0249c5 Revert "Use only 20 bits of address on the AXI lite port" gameboo 2024-09-11 20:02:35 +01:00
  • 90fb959788 Revert "implement C_GET_HIGH" Franz Fuchs 2024-10-23 17:39:32 +01:00
  • 303331cc8f implement C_GET_HIGH Yuecheng-CAM 2024-10-20 23:17:01 +01:00
  • 57fcf7a52a Revert "Revert "Use only 20 bits of address on the AXI lite port"" Jonathan Woodruff 2024-09-26 11:06:31 +01:00
  • 1cfc58c2cc Fix debug module reset state machine Peter Rugg 2024-09-16 16:10:02 +01:00
  • 6fc7327b93 Support narrow debug module register accesses Peter Rugg 2024-09-16 15:59:50 +01:00
  • aeae9b1f63 Busy the system bus when performing writes Peter Rugg 2024-09-16 16:00:11 +01:00
  • af8432d3f3 Return Abstract Command Error on unsupported CSRs Peter Rugg 2024-09-12 17:45:02 +01:00
  • 3b6b78db83 Fix src_Verifier directories not being included in TestRIG builds Peter Rugg 2024-09-16 16:12:40 +01:00
  • 47e12b8e65 Revert "Use only 20 bits of address on the AXI lite port" gameboo 2024-09-11 20:02:35 +01:00
  • c766187368 Use only 20 bits of address on the AXI lite port gameboo 2024-07-08 17:12:47 +01:00
  • 02ee2bdee0 Move RVFI toggle into Include_RISCY_Config.mk Samuel Stark 2024-05-28 16:11:14 +01:00
  • 7e1c9fdc98 Bump BlueStuff Peter Rugg 2024-05-21 16:22:00 +01:00
  • a5353f8f0f Bump BlueStuff Peter Rugg 2024-05-21 16:16:55 +01:00
  • 1f382b1563 Add license again to TourPred.bsv Franz Fuchs 2024-05-18 17:12:43 +01:00
  • 3e4dd64673 Merge pull request #27 from CTSRD-CHERI/CHERI_unified_makefile Jonathan Woodruff 2024-05-17 11:29:20 +01:00
  • 1b9d498e95 Standardise on using underscores in directory names in makefiles. Jonathan Woodruff 2024-05-17 11:21:42 +01:00
  • 2c648eb1ed Restructure makefiles so that all common and branch-specific flags/files are in Include_RISCY_Config.mk so that this can be included from an external repo without replicating Toooba branch-specific flags in that repo. Jonathan Woodruff 2024-05-10 18:00:21 +01:00
  • 3b7cc5261a Merge pull request #23 from CTSRD-CHERI/faf28_konata Franz Fuchs 2024-04-16 16:45:28 +01:00
  • 3532d44d56 Performed merge with CHERI Franz Fuchs 2024-04-16 16:42:37 +01:00
  • 598ac6574e Added working Konata support Franz Fuchs 2024-04-08 13:13:27 +01:00
  • 449070e347 Copied over preliminary Konata support from 89b0c37a7b Franz Fuchs 2024-04-08 10:59:33 +01:00
  • 9e4c8e54e1 Merge branch 'CHERI' into jdw57_getIssueLd_simplify Jonathan Woodruff 2024-04-15 09:14:31 +01:00
  • 70b82fb164 Insert deburster again on the vcu118-specific wrapper, as this design is known to work for the vcu118, or specifically, using the width converter. Jonathan Woodruff 2024-04-05 14:06:42 +01:00
  • 854e8e5bfb Another experiment to see if we can resolve the vcu118 build. This one puts the in-order shim before the width converter. Jonathan Woodruff 2024-04-05 10:54:39 +01:00
  • 8990ae56ed Revert "Potential workaround for issue with vcu118 memory bus error." Jonathan Woodruff 2024-04-05 10:44:50 +01:00
  • f86ea0203d Potential workaround for issue with vcu118 memory bus error. Just use the same ID for all outstanding requests such that all requests are in-order. Previously we were working fine with requests serialised; requests are now fully pipelined and out-of-order. This change should roll back to in-order, but still pipelined. This only affects the top-level used in the GFE (vcu118). This design is working on the DE10 setup, so the issue is not believed fundamental with CoreW. Jonathan Woodruff 2024-04-04 14:09:16 +01:00
  • 6f8c371a5c Roll back DTlB to two cycles for timing on DE10. Jonathan Woodruff 2024-03-25 12:52:51 +00:00
  • e0eefbcfd0 Be a little more careful with outstanding requests. Jonathan Woodruff 2024-03-18 09:10:55 +00:00
  • 235f025db8 Bump Bluestuff. Jonathan Woodruff 2024-02-20 14:19:46 +00:00
  • dd076fb189 Bump BlueStuff Peter Rugg 2024-02-16 17:04:13 +00:00
  • 271bc9c0e8 Experimentally remove deburster. This thing has a seraliser in it that serialises memory accesses, which is a disaster for performance. Jonathan Woodruff 2024-02-16 09:50:07 +00:00
  • 15fd2a4009 fixed compiler error for use of calloc Franz Fuchs 2024-02-08 15:31:42 +00:00
  • 6838b02274 Move to 4-way L1 caches to reduce area usage of splitting data ways into seperate BRAMs. Jonathan Woodruff 2024-02-05 09:40:15 +00:00
  • 0784902e45 Tune the instruction fetch FIFO to the lower-latency ICache. Jonathan Woodruff 2024-02-02 13:26:15 +00:00
  • b65994c00c Include the new single-cycle CCPipe as a seperate implementation, and use it only in the L1 caches so that the L2 cache can have lower resource utilisation and better timing. (Resource utilisation is up about 5% with the new design, and it's not necessary for the L2 cache.) Jonathan Woodruff 2024-02-02 11:50:45 +00:00
  • ccc71952bf Use forwarding BRAMs in L2 Cache. Duh; this is required for the new CCPipe structure. Jonathan Woodruff 2024-02-01 13:44:36 +00:00
  • 7608543da5 Move back to more traditional implementation of the forwarded BRAM, which also workst. Jonathan Woodruff 2024-02-01 10:07:48 +00:00
  • 3416040a74 Forward using a working forwarding memory rather than logic in CCPipe. This design runs CoreMark successfully. Jonathan Woodruff 2024-01-31 13:28:49 +00:00
  • 0e87595d73 Work toward eliminating a cycle of cache latency by doing data lookup in parallel with tag lookup. Jonathan Woodruff 2024-01-31 10:15:51 +00:00
  • 8e4848c4bc Turn off tracing in instruction fetch. Jonathan Woodruff 2024-01-26 16:32:16 +00:00
  • be26ac9f79 Fix a typo in a comment. Jonathan Woodruff 2024-01-26 16:31:49 +00:00
  • 9baadf58f3 Tune the size of the fetch pipeline fifos. This appears to make a 3% performance improvement in CoreMark. Jonathan Woodruff 2024-01-26 16:02:18 +00:00
  • e873bbd553 Clean up Fetch stage optimisations. This includes removing references to Fetch3, which no longer exists since Fetch2 and Fetch1 are merged (Fetch3 is now Fetch2). Jonathan Woodruff 2024-01-26 15:14:03 +00:00
  • ca4e120a6c Use DReg instead of Reg, as intended. Jonathan Woodruff 2024-01-22 12:06:39 +00:00
  • b586937953 Fix RVFI_DII by only going to the next ID when the instruction fetch is going ahead. Jonathan Woodruff 2024-01-22 11:38:52 +00:00
  • 640f330d7d Briefly report flush when vm_info has a change in the itlb to give an opportunity to flush the buffered translations. Jonathan Woodruff 2024-01-19 11:48:04 +00:00
  • d30bd71e72 Allow consuming TLB response while TLB is being flushed. Jonathan Woodruff 2024-01-18 13:04:21 +00:00
  • 83c756a4f4 Tidy up data mem pipeline changes to remove duplicated code. Jonathan Woodruff 2024-01-17 16:09:42 +00:00
  • 9d12fefda8 Remove commented-out code. Jonathan Woodruff 2024-01-17 14:30:34 +00:00
  • 829a787be5 Move to vector functions as it's cleaner. Jonathan Woodruff 2024-01-17 13:41:43 +00:00
  • 5a1ed7c57f Allow a vector of translations to be remembered. Just do 2 for now. Jonathan Woodruff 2024-01-17 13:21:38 +00:00
  • 4f91e54bd2 Properly remove pipline stage in fetch and use a seperate rule to do the proper TLB lookup if necessary. Jonathan Woodruff 2024-01-16 17:00:10 +00:00
  • eee5a2c23b Experiment with a zero-cycle TLB in instruction fetch as well. Jonathan Woodruff 2024-01-16 10:05:17 +00:00
  • 25a728b6d3 Optimise timing of TLB translation, ensuring that the translated address proceeds with minimal conditions to the output. Jonathan Woodruff 2024-01-16 09:50:35 +00:00
  • f9bf4ad856 Use default value on reset of Map. Jonathan Woodruff 2024-01-15 17:00:00 +00:00
  • 2c3c1da5c3 Solve last issue to allow doExeMem and doFinishMem. Jonathan Woodruff 2024-01-09 17:12:39 +00:00
  • 2f6a0980d9 Move all the work other than the TLB request out of doExeMem back to doRegReadMem. Jonathan Woodruff 2024-01-09 12:37:34 +00:00
  • 3e3531ffd5 Revert "A scheduling experiment to try to get doRegReadMem and doExeMem" Jonathan Woodruff 2024-01-09 11:54:53 +00:00
  • b733e05a86 A scheduling experiment to try to get doRegReadMem and doExeMem executing in the same clock cycle. It doesn't seem to work (yet). Jonathan Woodruff 2024-01-09 11:52:29 +00:00
  • 32d094082b Some tracing for performance in the memory pipeline. Also, add some ports to registers in DTLB to potentially allow single-cycle lookup. Jonathan Woodruff 2024-01-08 15:28:24 +00:00
  • 2d05514b66 An experimental simplification of the SplitLSQ, which I think works because the Memory pipeline only ever reads the getIssueLd interface in the same rule that it calls issueLd. Jonathan Woodruff 2023-12-12 17:29:27 +00:00
  • 8cd6e8db87 Bump BlueStuff Peter Rugg 2023-10-31 13:25:35 +00:00
  • 9dae87b505 Bump cheri-cap-lib gameboo 2023-08-30 21:28:39 +01:00
  • e9c2db4e60 Allocate mem_buf dynamically in elf_to_hex Peter Rugg 2023-10-24 18:09:40 +01:00
  • d04c8ea3a9 Tidy section formatting so that it better exports to asciidoctor. Simon Moore 2023-08-30 18:26:47 +01:00
  • da473192c7 Bump BlueStuff gameboo 2023-08-24 17:18:00 +01:00
  • 5ca4843be1 Bump BlueStuff gameboo 2023-08-21 14:30:26 +01:00
  • 16592ae29a Bump BlueStuff Peter Rugg 2023-08-16 18:30:27 +01:00
  • 43378ee339 Bump BlueStuff gameboo 2023-07-25 16:05:15 +01:00
  • 4acbe2f43b Fix build error with SPEC contracts Peter Rugg 2023-07-17 17:38:57 +01:00
  • 5818a886dd Factor out delay shim Peter Rugg 2023-07-13 16:06:14 +01:00
  • d509ab0fab Mask off address bits in latency shim Peter Rugg 2023-07-12 17:06:03 +01:00
  • 5414a13d3b Add prints for latency rules Peter Rugg 2023-07-12 17:05:47 +01:00
  • f71f650023 Allow dynamic latency config Peter Rugg 2023-07-12 15:34:36 +01:00
  • d17d3135bb Add error clear implementation for delayShim Peter Rugg 2023-07-12 15:34:12 +01:00
  • 23b471e0ae Increase number of outstanding transactions in delayShim Peter Rugg 2023-07-12 15:33:48 +01:00
  • 1a94699de6 Delay non-burst channels Peter Rugg 2023-07-12 11:09:54 +01:00
  • e6370f46f6 Remove unnecessary type Peter Rugg 2023-07-12 11:09:42 +01:00
  • f7755d0e58 Increase DRAM latency for realism Peter Rugg 2023-07-11 16:38:34 +01:00
  • 2584c96095 Bump BlueStuff gameboo 2023-07-13 15:35:20 +01:00
  • 561683343d Add a mean to configure starting PC dynamically at start of simulation gameboo 2023-07-13 15:34:08 +01:00
  • f00d924528 Bump BlueStuff gameboo 2023-07-04 17:08:16 +01:00
  • 373b849d29 Merge branch 'tag-clear' into CHERI Peter Rugg 2023-06-27 11:38:42 +01:00
  • ec4eacac9c Fix CSetAddr tag clear bug Peter Rugg 2023-06-26 18:01:56 +01:00
  • 3ebf537f71 Tidy up tracing options, including using RVFI when building for bluesim (which I'm sure we had meant to be doing?). Jonathan Woodruff 2023-06-23 13:09:38 +00:00
  • c1f631eed3 Bump BlueStuff gameboo 2023-06-22 17:20:45 +01:00
  • b3a75cfeac Bump BlueStuff and make use of Makefile fragment gameboo 2023-06-22 16:40:23 +01:00
  • 11d5d403ed Bump BlueStuff gameboo 2023-06-22 16:02:19 +01:00
  • 78b4554f5e Bump BlueStuff gameboo 2023-06-21 16:00:11 +01:00