bbaa2ab233
made low-impact contract flags the standard ones
Franz Fuchs
2022-07-08 17:18:16 +01:00
1bea2c6af2
added missing character to Makefile
Franz Fuchs
2022-07-06 08:31:43 +01:00
0dd65a937f
enabled full BSC build
Franz Fuchs
2022-07-05 12:09:26 +01:00
92b096472a
do configuration for base protection version of Toooba
Franz Fuchs
2022-07-01 10:19:26 +01:00
45b3eaf09c
correct SSITH Makefile
Franz Fuchs
2022-06-30 12:57:07 +01:00
c85b13c5af
added MELTDOWN_CF ifdef and enabled it
Franz Fuchs
2022-06-30 12:55:53 +01:00
9b0e5c4334
Merge branch 'scc' into CHERI
Franz Fuchs
2022-06-30 12:34:15 +01:00
82adf5e869
attempt to get new performance numbers
Franz Fuchs
2022-06-29 17:42:38 +01:00
40cfd0e97c
removed PUSH_DELAY from gfe-synth build
Franz Fuchs
2022-06-16 08:56:07 +01:00
1ab18ab6ee
full BSC protection for gfe-synth build
Franz Fuchs
2022-06-15 06:07:36 +01:00
fb259583dc
Attempt to clear tag on exception path before forwarding.
Peter Rugg
2022-06-15 00:53:55 +01:00
f8b97ceb6a
corrected ifdef in STLPred.bsv
Franz Fuchs
2022-06-09 15:24:10 +01:00
b79a228093
added no prediction STL predictor
Franz Fuchs
2022-06-08 12:23:35 +01:00
891567f3aa
added STL predictor module and moved state from SplitLSQ to it
Franz Fuchs
2022-06-08 12:04:25 +01:00
e37339b147
Return 0 on CToPtr if authority tag unset
Peter Rugg
2022-05-16 11:42:35 +01:00
338b98e0d2
Remove tag-assertions when manipulating capabilities
Peter Rugg
2022-05-16 11:40:13 +01:00
b113d05095
Prioritise misaligned over RVFIDII load access fault
Peter Rugg
2022-05-18 14:59:31 +01:00
fd639f4b22
added typedef for static number in Ras.bsv
Franz Fuchs
2022-05-14 17:16:40 +01:00
8ba929438d
Fix cloadtags in LLC
Peter Rugg
2022-03-24 23:51:59 +00:00
6d4644ce73
Add tag-only state to MESI and interface with tagOnlyReq of tag controller
Peter Rugg
2021-10-25 17:29:39 +01:00
25013c9713
Revert to including performance improvements by default.
Jonathan Woodruff
2022-03-29 10:26:35 +00:00
c273314084
Remove all BSC protections in an attempt to get a baseline bitfile for that work.
Jonathan Woodruff
2022-03-29 10:17:12 +00:00
163ca1d099
Use only parameters that improve performance.
Jonathan Woodruff
2022-03-25 14:08:43 +00:00
9bfaf4cbf0
Swap poliarity of prediction for comparison with upstream.
Jonathan Woodruff
2022-03-25 14:03:06 +00:00
6d7f95571f
Merge remote-tracking branch 'origin/CHERI' into jdw57_prediction
Jonathan Woodruff
2022-03-25 13:06:22 +00:00
ad7bcbb559
Temprarily remove all protections for a baseline bitfile.
Jonathan Woodruff
2022-03-25 11:09:32 +00:00
3248e42485
Temporarily turn off late push so we can run benchmarks for non-push case.
Jonathan Woodruff
2022-03-21 10:14:08 +00:00
3cdc2d31c8
Experimentally increase delay before reset.
Jonathan Woodruff
2022-03-21 10:13:48 +00:00
09db91f8c8
Reset counter if head becomes valid.
Jonathan Woodruff
2022-03-16 11:39:57 +00:00
d0c1d97a2a
Print RVFI packets in RVFI_DII also
Peter Rugg
2022-03-15 10:03:43 +00:00
7b78c0ed7b
Delay returns (up to 10 cycles) if there is an outstanding push.
Jonathan Woodruff
2022-03-14 18:45:34 +00:00
a6b39b58a1
Clean up prints
Peter Rugg
2022-03-11 10:23:31 +00:00
37a7745f1a
Fix a few errors in the previous commit, and importantly, make the "push" from writeback just a write to the location that was meant to push to, rather than the current head.
Jonathan Woodruff
2022-03-10 11:04:54 +00:00
00c0021479
Enable RVFI by default for bluesim builds
Peter Rugg
2022-03-09 14:58:11 +00:00
d005d4ea61
Bump BSV-RVFI-DII
Peter Rugg
2022-03-09 14:55:46 +00:00
a6976c0071
Fix RVFI-only build
Peter Rugg
2022-03-09 14:50:48 +00:00
9d68d877d9
Move to much simpler design. Just update the head in Decode, and write data from Execute. A loop calling from the same place will at least find the correct address. Also, the bad fixup interaction is solved.
Jonathan Woodruff
2022-03-09 12:32:01 +00:00
bbdcf6dde9
A more sophisticated RAS protection delay. Saturate down, and also predict with old push value if there is more than 6 cycles of delay.
Jonathan Woodruff
2022-03-08 15:17:54 +00:00
064cd22114
Inteligently delay Decode (for up to 8 cycles) if we encounter a pop while waiting for a push.
Jonathan Woodruff
2022-03-07 17:52:11 +00:00
56c0ca328b
Added missing update due to changing version of BlueStuff
Franz Fuchs
2022-02-28 13:03:00 +00:00
6d65de5c88
Experimentally remove delayed RSB_PUSH for synthesis.
Jonathan Woodruff
2022-02-24 11:49:35 +00:00
6ea972931d
Add missing verilog file that is inadvertantly used.
Jonathan Woodruff
2022-02-23 16:46:43 +00:00
28646b252d
Add BSC protections to the hardware makefile.
Jonathan Woodruff
2022-02-23 11:43:41 +00:00
c17874bdba
Add options to disable each of 5 aspects of enforcment of the Branching Speculation Contract.
Jonathan Woodruff
2022-02-22 16:21:53 +00:00
90f236aab1
Bumped BlueStuff, TagController and BSV-RVFI-DII
Franz Fuchs
2022-02-21 14:39:44 +00:00
f46b961674
Bumped TagController
Franz Fuchs
2022-02-21 09:19:25 +00:00
e889bb95fa
Add a "delay" for fixups after a push. A push updates the head pointer from Execute, but the instructions between Decode and execute will have an out-of-date head pointer. If a branch in that window mispredicts, it will get the head pointer out of sync by resetting it to ignore the push. By delaying by one branch, we seem to eliminate over 60% of the misses, and reduce the cycle overhead from 0.5% to 0.2% in CoreMark, and still well ahead of the baseline with no fixup.
Jonathan Woodruff
2022-02-18 18:00:02 +00:00
75d1afe8b4
Only push to RAS when the linking instruction is non-speculative. That is, don't push in Decode, push from the training structure coming from Execute, which is delayed until the instruction that issued it is non-speculative.
Jonathan Woodruff
2022-02-18 13:22:02 +00:00
2b9ebb5b40
Ugly hack to avoid redirection epoch from being killed by the killAll. Commit stage redirections are post-prediction and should need to somehow be treated specially in the SpecFifo for epochs in the fetch stage. They are post-commit, so should be unkillable somehow. I guess SpecFifos are not meant to hold post-commit state currently.
Jonathan Woodruff
2022-02-16 12:23:05 +00:00
4961d321b9
Merge branch 'CHERI' into jdw57_prediction
Jonathan Woodruff
2022-02-16 10:10:00 +00:00
e118e7c0ee
Merge branch 'CHERI' into jdw57_schedule_experiments_III
Jonathan Woodruff
2022-02-14 16:01:47 +00:00
05df76073b
Revert some unintended changes from the last commit.
Jonathan Woodruff
2022-02-01 11:08:37 +00:00
01132d165a
Enable tracing of physical addresses for RVFI (if PADDR_RVFI is defined). This is done by adding a vector of padder lookup interfaces to the load store queue. This should help with targeted memory translation debugging, and also with compatability with the current Sail RVFI implemenation which is probably incorrect with respect to the RVFI spec which calls for virtual addresses in the maddr field.
Jonathan Woodruff
2022-02-01 09:10:48 +00:00
ad5d5aca0d
Also pause branch execution when there is a pending wrong speculation.
Jonathan Woodruff
2022-01-12 13:13:39 +00:00
a56deab46c
Simpelest strategy for making wrongSpec not conflict with loads of rules. This triggers some assertions in the ROB what should be dealt with properly if this is going to work.
Jonathan Woodruff
2021-12-09 12:27:57 +00:00
4fbb7b5648
A version that seems to actually run. The buffer in GlobalSpecUpdate has to be a SpecFifo.
Jonathan Woodruff
2022-01-11 00:06:49 +00:00
c1c4a46b1e
Simpelest strategy for making wrongSpec not conflict with loads of rules. This triggers some assertions in the ROB what should be dealt with properly if this is going to work.
Jonathan Woodruff
2021-12-09 12:27:57 +00:00
886854faec
Merge branch 'CHERI' into jdw57_schedule_experiments_III
Jonathan Woodruff
2022-01-31 11:52:14 +00:00
1ee961bb83
Simplify timing optimisation by including in the root of the original loop.
Jonathan Woodruff
2022-01-27 17:13:11 +00:00
4cfd652b0d
Use mkRegOR in register file.
Jonathan Woodruff
2022-01-25 20:42:16 +00:00
6ea5d34d06
Bump Bluestuff.
Jonathan Woodruff
2022-01-25 17:05:34 +00:00
678c5bcf49
Fix RVFI_DII which had inadvertently been broken.
Jonathan Woodruff
2022-01-20 17:35:16 +00:00
ef6945cc07
More readable version of previous optimisation, with input from Alexandre.
Jonathan Woodruff
2022-01-19 15:28:45 +00:00
e497091e18
A timing optimisation for the direction predictor. Add a "nextPc" interface so that lookup can begin in the previous cycle. Remove the "pc" operands in the vector of lookup interfaces, but rather derive the PC from lookup from the first PC being looked up in that cycle. That is, by adding 4*(interface number) to the beginning lookup PC. As this might not actually be the PC of the instruction, pass the index you used with the training info so that you are certain to train with the same index you looked up.
Jonathan Woodruff
2022-01-18 11:05:09 +00:00
dac5c99100
Perform a number of decode and prediction operations unconditionally on the vector of instructions outside of the decode loop to improve timing. Specifically, the branch direction prediction is lifted out and depends only on whether there is agreement between direction prediction and a branch being predicted by fetch, not on the actual predicted next PC. This appears to keep the global history clean enough to perform on-par with the old design in CoreMark. This is a general timing improvement and should be upstreamed.
Jonathan Woodruff
2022-01-14 11:53:40 +00:00
7009087cd4
Merge branch 'CHERI' into jdw57_schedule_experiments_III
Jonathan Woodruff
2022-01-13 11:15:09 +00:00
1f8181d595
Move to (recently merged) non-pipelined Divide.
Jonathan Woodruff
2022-01-13 11:14:20 +00:00
37f6dbde93
Timing optimisation for Tournament Predictor. Start global-history-indexed lookups in the previous cycle. This is a general timing optimisation that should be pushed upstream at some point.
Jonathan Woodruff
2022-01-12 16:08:33 +00:00
d1de1ab952
Also pause branch execution when there is a pending wrong speculation.
Jonathan Woodruff
2022-01-12 13:13:39 +00:00
88cca33a84
Merge branch 'CHERI' into jdw57_schedule_experiments_III
Jonathan Woodruff
2022-01-11 00:09:01 +00:00
7ba5ddec8b
A version that seems to actually run. The buffer in GlobalSpecUpdate has to be a SpecFifo.
Jonathan Woodruff
2022-01-11 00:06:49 +00:00
1e9ee9d121
Simpelest strategy for making wrongSpec not conflict with loads of rules. This triggers some assertions in the ROB what should be dealt with properly if this is going to work.
Jonathan Woodruff
2021-12-09 12:27:57 +00:00
1d6633f423
Buffer redirection from Commit to reduce conflicts in the pipeline. This is a general improvement, and should be upstreamed to master if there are no issues discovered.
Jonathan Woodruff
2022-01-10 17:18:01 +00:00
e600fd7d38
Delay BTB update by a cycle for timing. This should not be a primary degredation of performance since the redirection gets on seperately from this update which will only affect future predictions.
Jonathan Woodruff
2022-01-08 10:15:22 +00:00
b84562a027
Improve scheduling for LatencyTimer to improve timing path discovered on DE10.
Jonathan Woodruff
2022-01-07 09:52:43 +00:00
f619f4b0a1
Make the associative BTB compressed. That is, only store the bottom 16 bits of the target if the upper bits of pc and nextPc match. Have a single "way" dedicated to full targets.
Jonathan Woodruff
2021-11-15 11:50:57 +00:00
Alexandre Joannou