c37c611522
Merge branch 'CHERI' into faf28_sbc_jumps
Franz Fuchs
2021-07-08 17:14:27 +01:00
224ab35679
Completed introduction of new build flag
Franz Fuchs
2021-07-08 15:38:19 +01:00
4ba377366a
Introduced new build flag for transient-execution testing contracts
Franz Fuchs
2021-07-08 15:28:54 +01:00
849d5c57f8
Fix condition where Queue can remain "empty" when there were outstanding indices due to the head-1 element happening to match new requests. This leads to "remove" when empty, leading to being "almostFull" when there are no outstanding users that will remove anything.
jon
2021-07-07 11:30:06 +01:00
994321e527
Potential fix for lockup condition where the (undefined) bits of instruction returned for an invalid fetch (that is, with a valid cause) indicate a 2-fragment instruction but where a second fragment is not available.
jon
2021-07-07 11:26:34 +01:00
db6a91e0fd
mad Maps flush on reset
Franz Fuchs
2021-07-06 15:19:37 +01:00
2eb2202acd
Added checking for wild exceptions in MemExePipeline including adding an addtional port to the ROB for reading ppc/orig_inst
Franz Fuchs
2021-06-28 07:34:57 +01:00
b48a161fda
Experimentally remove repeated write of rg_m_halt_req register.
jon
2021-06-25 17:31:10 +01:00
fec16f64c8
Added first attempts for counting wild exceptions
Franz Fuchs
2021-06-25 15:44:29 +01:00
f83d7b1554
Added missing ifdefs
Franz Fuchs
2021-06-24 08:35:21 +01:00
0c80ac30bb
Corrected wild jumps type to SupCnt
Franz Fuchs
2021-06-23 15:36:45 +01:00
c9df8da1b1
Corrected SBC counting
Franz Fuchs
2021-06-23 12:47:34 +01:00
23913a50e0
Improved code for detecting SBC violations
Franz Fuchs
2021-06-23 08:00:42 +01:00
76cdc13a50
Added counting code for return instructions
Franz Fuchs
2021-06-22 18:01:32 +01:00
8f45238b5d
implemented method returning the trans exe events
Franz Fuchs
2021-06-22 08:49:40 +01:00
06e0a3d810
corrected SBC jumps counting
Franz Fuchs
2021-06-22 08:40:27 +01:00
4a50ae5bc8
Fix some misplaced ifdefs
Peter Rugg
2021-06-14 15:13:35 +01:00
a60bed404a
Added new counting for branching instructions
Franz Fuchs
2021-06-11 17:09:21 +01:00
dce934500d
Added counter mechanism for wild jumps
Franz Fuchs
2021-06-11 10:47:15 +01:00
c51af07278
Collect all architectural jump targets (the first 16) in a bag to enable verifying properties
Franz Fuchs
2021-06-10 18:55:00 +01:00
2572fdceba
Added documentation for rename counter and removed unnecessary display messages
Franz Fuchs
2021-06-08 15:03:12 +01:00
914eb17550
Added microarchitectural counter for renamed instructions
Franz Fuchs
2021-06-08 13:18:57 +01:00
c1cdd9e5e1
Corrected tag controller events based on EventsCacheCore
Marno van der Maas
2021-06-07 17:53:24 +01:00
8bd8ee6310
Doc update for tag controller performance monitor addresses based on commit d7a492b48f
Marno van der Maas
2021-06-07 17:37:13 +01:00
d7a492b48f
Move to Flute standard placement for Tag Cache events, which is just the raw order from the CacheCore events.
jon
2021-06-01 15:17:25 +01:00
10f0807a9b
Fix arbitration for non-power-of-two numbers of sources
Peter Rugg
2021-05-28 14:37:24 +01:00
bf911326e3
Fix some arbitration bugs
Peter Rugg
2021-05-28 12:36:06 +01:00
46b1519cb0
mkXBar: Simplify as fallback case handles priority case correctly
Jessica Clarke
2021-05-28 02:57:12 +01:00
d78a2799d3
Fixed small mistake pointed out by Peter(pdr32)
Franz Fuchs
2021-05-12 10:46:07 +01:00
fcea3a1f4e
included suggestions from Peter (pdr32)
Franz Fuchs
2021-05-11 19:28:49 +01:00
f6bd0b0e1b
first attempts to fix inhibit mismatch
Franz Fuchs
2021-05-11 14:13:02 +01:00
1620aae1de
Bump Bluestuff.
jon
2021-05-08 07:31:22 +01:00
0a7e77230e
Style improvements (suggested by jrtc27)
Peter Rugg
2021-05-05 13:29:42 +01:00
7e77b2314b
Clarify precedence in VM permission check
Peter Rugg
2021-05-05 12:07:28 +01:00
e7258f0f22
Plumb through info on whether a load is capWidth to the TLB
Peter Rugg
2021-05-05 12:06:58 +01:00
b8d86df2d0
Guard Meltdown_CF protection (such as it is) with ifdef rather than just comment it out.
jon
2021-05-04 11:29:36 +01:00
2dccf1b557
Add (not-enabled-by-defaul) Meltdown-CF fix which resolves CUnseal, but not any of the ones that require a bounds-check. This isn't enabled by default so that we can evaluate the seriousness of the vulnerabilities.
jon
2021-04-29 17:46:39 +01:00
48e22af43e
Factor out PTE cap invalid check
Peter Rugg
2021-04-29 13:22:58 +01:00
005ba1bd6f
Add LoadCapPageFault exception cases
Peter Rugg
2021-04-29 09:55:38 +01:00
1eef5d2979
Still advance the DII stream on instruction fetch PTE fault (with jrtc27)
Peter Rugg
2020-11-10 15:41:56 +00:00
3b07a2a17c
Add revocation 3.0 bits
Peter Rugg
2020-11-03 00:46:58 +00:00
55da2986af
Set mtval for excStoreCapPageFault-s correctly
Nathaniel Filardo
2021-04-26 02:07:10 +01:00
ac89600601
Add missing TSO dummy store buffer to component.xml
Peter Rugg
2021-04-23 16:33:04 +01:00
10b5cd7ad7
Switch to TSO
Peter Rugg
2021-04-22 18:22:02 +01:00
9b88dc4ce0
Bump TagController to version with 128K, not 1M.
jon
2021-04-22 10:35:18 +01:00
702eab2ee4
Bump to latest version of TagController. We failed to bump in this repo for thet last size increase of the TagCache, but there was also a misunderstanding about what size we were getting. This one moves from 64KiB 2-way to 128KiB 4-way.
jon
2021-04-21 12:26:19 +01:00
7cefaacb86
Remove wayward disabling of consistency flush case for the weak memory model.
jon
2021-04-21 10:44:31 +01:00
280ace318e
Bump TagController to quadruple the size again.
Jonathan Woodruff
2021-04-15 14:27:41 +00:00
86afb7e68e
Add counter for LL writebacks (in the ST_MISS field).
jon
2021-04-12 16:20:14 +01:00
53549e0dbc
Set number of cores using RISCY config instead of manual define
Peter Rugg
2021-04-12 13:10:12 +01:00
2c41fcd7fb
Fix bug and improve expression by using Int.
jon
2021-04-12 12:48:49 +01:00
4776bc0a11
Double-train on killing a load (still decrement by one on success). This combo got the best performance overall (I tested triple and quadruple training).
jon
2021-04-12 06:34:16 +01:00
8e3fd534f9
Do negative training when we encounter a load that has previously been killed, but was not killed this time.
jon
2021-04-10 08:47:05 +01:00
aa9e57ce10
Fix bug so that we actually start at minBound. (Map defaults to unpack(0), so for an Int, our first updateFunc will add one to zero and it won't be much different than before.)
jon
2021-04-10 07:54:39 +01:00
6b871c0442
Use a saturating add before being conservative with issuing loads.
jon
2021-04-09 16:20:27 +01:00
fcea5365f6
Initial implementation CLoadTags
Peter Rugg
2021-04-08 16:04:06 +01:00
0be771df4c
Bump TagController to one with 32KiB cache.
jon
2021-04-08 14:40:49 +01:00
b232272ad1
Treat CCSeal with an out-of-bounds capability as a move
Peter Rugg
2021-04-08 13:08:46 +01:00
12ac14c1ca
Move to config registers here as this affects scheduling.
jon
2021-04-07 17:47:49 +01:00
3f059cbd94
Added note on bsc-contrib dependency to SSITH readme
Marno van der Maas
2021-04-07 11:53:48 +01:00
ad044689cb
added some of the performance counters in the L2 TLB
Franz Fuchs
2021-04-01 15:15:32 +01:00
6e157fff5a
Small improvement of BTB changes made by Jon and myself
Franz Fuchs
2021-04-01 09:08:47 +01:00
c17eb9e7c1
Finish propagating BTB name change from previous commit.
jon
2021-04-01 09:04:31 +01:00
0701dea9a9
Preserve name for verilog so component.xml doesn't have to be fixed.
jon
2021-04-01 07:08:46 +01:00
4b531fac46
Made the hash size in the BTB configurable
Franz Fuchs
2021-03-31 17:46:27 +01:00
84271b2712
Changes to build (and run?) with TSO_MM.
jon
2021-03-29 12:03:27 +01:00
5e687a972a
Slight cleanups from review with Alexandre.
jon
2021-03-24 12:21:00 +00:00
07dd70d77b
Associative 2-way associative BTB. Also, 16-bit hashed tags. (This is because the only full-speed implementation required duplicating the tags). This implementation uses the MAP library, and a new BRAM instance of it.
jon
2021-03-24 09:56:25 +00:00
20e2249761
Make map associative in preparation for associative BTB. Also make jump alias predictor smaller and associative. (2x64 entries instead of 256 entries)
jon
2021-03-23 11:26:43 +00:00
2bfe25dfad
Update Map.bsv
Jonathan Woodruff
2021-03-22 20:28:34 +00:00
d351eeee11
Increase BTB to 1024 entries. (On FPGA we can make this as large as we like, but returns diminish. This one has a chance of being reasonable for ASIC I guess?)
jon
2021-03-22 18:20:22 +00:00
30bd5e7f46
Allow entries in the load kill predictor to be "False" so that they can be invalidated. Also invalidate entries "randomly" to prevent a steady-state of waiting for all stores to complete on 1/256 loads even when no aliasing is going on.
jon
2021-03-20 11:22:30 +00:00
791927f852
Prediction for whether a load will have an aliasing store.
jon
2021-03-15 15:57:16 +00:00
47cddd8ec9
Reverted back to using FPGA specific memory addresses
Marno
2021-03-19 15:54:53 +00:00
dbc1443bf2
Also using new tagsparams API in SSITH build
Marno
2021-03-19 15:30:11 +00:00
c38f0e8488
Using new tagparams.py that explicitly warns about overlapping tag and data memory regions
Marno
2021-03-19 11:22:40 +00:00
5d7b224d8b
Added TagTableStructure.bsv as dependency for .depends.mk in verilator build as well
Marno van der Maas
2021-03-18 11:36:46 +00:00
057964e940
Some more tagsparam makefile fixes
Peter Rugg
2021-03-18 11:06:17 +00:00
e759077259
Made sure TagTableStructure.bsv is present upon regenration of .depends.mk
Marno
2021-03-18 10:47:15 +00:00
e7d0a6adf6
Removing TagTableStructure.bsv and .depends.mk on clean
Marno
2021-03-17 16:53:03 +00:00
df6cc12abb
Removed TagTableStructure.bsv files from repo because these are now automatically generated
Marno
2021-03-17 16:01:16 +00:00
db57e909fc
Added calling tagsparams.py in Include_Common.mk
Marno
2021-03-17 15:56:03 +00:00
c5a0d38a63
Enabled HPM by default in builds/RV64ACDFIMSUxCHERI_Toooba_verilator/
Franz Fuchs
2021-03-16 13:19:47 +00:00
80fb97cc62
Take Bluestuff-ified Giraffe_IFC from Flute
Peter Rugg
2021-03-15 12:25:38 +00:00
395a9d1c02
Remove unused non-existent libraries from ssith Makefile
Peter Rugg
2021-03-15 11:26:24 +00:00
Franz Fuchs