Cheri-research/Toooba
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3636f6239a17ae04ce84f950b5c5dbda53eefb42
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459 Commits

Author SHA1 Message Date
Jonathan Woodruff
3636f6239a Use Matt's slightly cleaner version of the function. 2021-10-11 16:23:22 +00:00
Jonathan Woodruff
1b5a036c46 Two fixes: do a proper "all bits are the same" function, as well as 
prepare a capability target to pass back.
 2021-10-08 16:35:42 +00:00
Jonathan Woodruff
5d5bee3e08 Use an invalid virtual address when preventing prediction, and also 
detect invalid virtual addresses in the TLB and miss rather than proceed
with page walking.
 2021-10-08 11:00:11 +00:00
Jonathan Woodruff
cec55419f5 Merge branch 'CHERI' into jdw57-jr-bsc-safety 2021-10-08 09:50:45 +00:00
Jonathan Woodruff
3d0aee0af4 Remove some verbosity from the committed state. 2021-10-07 16:30:32 +00:00
Jonathan Woodruff
81a12b89cb Move to NonPipelinedSquareRooter to hopefully fit more 
deterministically.
We're still waiting for a fixed NonPipelinedDivider.
 2021-10-07 16:28:57 +00:00
Jonathan Woodruff
520b09a6ed Use less wierd default value. 2021-10-07 16:17:19 +00:00
Jonathan Woodruff
fe9e000f43 Merge branch 'CHERI' into jdw57-jr-bsc-safety 2021-10-04 08:37:56 +00:00
Franz Fuchs
db54d27368 Move import DReg::* into ifdefs 2021-10-01 16:54:17 +01:00
Jonathan Woodruff
c69acc2fc4 Don't predict next instruction for JR without a BTB prediction. 2021-09-30 12:20:40 +00:00
gameboo
9657339d87 "fix" non PERFORMANCE_MONITORING build 2021-09-29 18:09:06 +01:00
Franz Fuchs
87977461a6 Merge branch 'CHERI' of github.com:CTSRD-CHERI/Toooba into CHERI 2021-09-29 14:23:20 +01:00
Franz Fuchs
cf8bfdc4a8 Merge branch 'faf28_hpm_consistency' into CHERI 2021-09-29 14:04:08 +01:00
Franz Fuchs
db9b5c7f54 re-integrated TagController 2021-09-24 11:39:23 +01:00
Peter Rugg
8ef44b0a6c Workaround single step wedges by not waiting for flush before halting 2021-09-24 10:33:58 +00:00
Franz Fuchs
4cfac08bca Bumped BlueStuff and made necessary adaptations 2021-09-23 15:25:46 +01:00
Franz Fuchs
9ea66bed86 Merge pull request #18 from CTSRD-CHERI/faf28_hpm_consistency 
Using HPM information from one central struct
 2021-09-20 13:21:52 +01:00
Franz Fuchs
9320e53720 Bumped RISCV_HPM_Events made minor changes 2021-09-17 10:38:48 +01:00
Jonathan Woodruff
c489a177d4 Fix type error. 2021-09-08 10:23:29 -05:00
Jonathan Woodruff
08231b7e5c Hopefully don't wedge on ifetch bus error. 
We think that we were wedging on IFetch bus error.
It appears that we didn't make the last instruction fragment valid in the bus error case, and expect that this path was not previously exercised.
This change returns 0s (to hopefully make the error less subtle) in exactly the right number of fragments.
 2021-09-08 10:11:25 -05:00
Franz Fuchs
b25d70a8cc performed corrections for CONTRACTS_VERIFY 2021-09-07 08:15:03 +01:00
Franz Fuchs
bc7eed67ab Did more cleaning up 2021-09-06 15:55:28 +01:00
Franz Fuchs
4c9d89e936 Performed a bit of cleaning up 2021-09-06 13:33:13 +01:00
Franz Fuchs
e33b4021d8 Integrated generateHPMVector function 2021-09-03 17:37:43 +01:00
Franz Fuchs
61d788ebc7 define No_Of_Evts in StatCounters 2021-09-03 14:14:32 +01:00
Franz Fuchs
20e67971a5 Use type EventsCacheCore instead of Vector#(7, Bit#(1)) 2021-09-02 16:10:55 +01:00
Franz Fuchs
9f615e4481 initial changes for HPM consistency 2021-09-02 14:50:17 +01:00
Robert Norton
0970951184 Fix decoding of lr / sc with explicit bounds. 
When decoding {lr,sc}.{b,h,w,d,c,q}.{ddc,cap} the IType was not being set correctly. For sc we also need to set the destination register.
 2021-09-01 10:16:49 +01:00
Peter Rugg
dbb6043760 Don't compile SelfInv* without define 2021-08-16 14:42:59 +01:00
Robert Norton
7e2a946c4c Fix incorrect check for permitStoreLocalCap in capChecksMem. 
The check was missing a NOT and was actually checking for permitStoreGlobalCap.
 2021-08-05 12:19:50 +01:00
Robert Norton
5b23f4cea0 Fix incorrect checks in capChecksMem. 
These checks were broken in several ways:

1) a missing 'else' inverted the priority of PermitStoreViolation vs. PermitStore[Local]Cap exceptions
2) another missing 'else' inverted the priority of PermitStoreCap and PermitStoreLocalCap exceptions
3) No store checks were performed when mem_func == Amo because of the preceding if clause for loads

I decided to flatten the nested if statements by pulling out the conditions into boolean local variables. Hopefully this makes it clearer (as well as fixing the bugs).
 2021-08-05 09:33:52 +01:00
Robert Norton
ff0221f6bc Fix CHERI Exception numbering to match spec. 
It looks like PermitUnsealViolation and PermitSetCIDViolation were accidentally renumbered to fill in the gap left by the retired CCallAcessIDCViolation.
 2021-08-02 12:15:05 +01:00
Franz Fuchs
cc25ee69d3 Check in Rename stage for nextPcs of Traps 2021-07-26 07:02:21 +01:00
Franz Fuchs
2831cd7ee3 Changed size of bags for testing SBC to 32 2021-07-16 14:51:26 +01:00
Franz Fuchs
483cef8852 Removed unnecessary display statements 2021-07-12 14:55:07 +02:00
Franz Fuchs
7b1b564d62 Added missing ifdef 2021-07-12 13:30:53 +01:00
Franz Fuchs
c37c611522 Merge branch 'CHERI' into faf28_sbc_jumps 2021-07-08 17:14:27 +01:00
Franz Fuchs
224ab35679 Completed introduction of new build flag 2021-07-08 15:38:19 +01:00
Franz Fuchs
4ba377366a Introduced new build flag for transient-execution testing contracts 2021-07-08 15:28:54 +01:00
jon
849d5c57f8 Fix condition where Queue can remain "empty" when there were outstanding 
indices due to the head-1 element happening to match new requests.
This leads to "remove" when empty, leading to being "almostFull" when
there are no outstanding users that will remove anything.
 2021-07-07 11:34:29 +01:00
jon
994321e527 Potential fix for lockup condition where the (undefined) bits of 
instruction returned for an invalid fetch (that is, with a valid cause)
indicate a 2-fragment instruction but where a second fragment is not
available.
 2021-07-07 11:34:29 +01:00
Franz Fuchs
db6a91e0fd mad Maps flush on reset 2021-07-06 15:19:37 +01:00
Franz Fuchs
2eb2202acd Added checking for wild exceptions in MemExePipeline including adding an addtional port to the ROB for reading ppc/orig_inst 2021-06-28 07:34:57 +01:00
jon
b48a161fda Experimentally remove repeated write of rg_m_halt_req register. 2021-06-25 17:31:10 +01:00
Franz Fuchs
fec16f64c8 Added first attempts for counting wild exceptions 2021-06-25 15:44:29 +01:00
Franz Fuchs
f83d7b1554 Added missing ifdefs 2021-06-24 08:35:21 +01:00
Franz Fuchs
0c80ac30bb Corrected wild jumps type to SupCnt 2021-06-23 15:36:45 +01:00
Franz Fuchs
c9df8da1b1 Corrected SBC counting 2021-06-23 12:47:34 +01:00
Franz Fuchs
23913a50e0 Improved code for detecting SBC violations 2021-06-23 08:00:42 +01:00
Franz Fuchs
76cdc13a50 Added counting code for return instructions 2021-06-22 18:01:32 +01:00