This includes replacing register read values with nullCap if reading x0, which is generally necessary.
This is more-or-less using a new mechanism which shouldn't actually be necessary if the default value in the register file is nullCap.
(In RVFI_DII, we initialise with the almightyCap instead.)
This required makeing the Exception type wider by one.
The actual "inBounds" check is currently implemented in the reorder buffer rows, which duplicates the logic ~80 times (number of outstanding instructions), which isn't ideal, but it's using the quick in-bounds check that only compares the mantissa-sized things.
Also move to SetAddrUnsafe, as is traditional for setting the address of PCC where we do proper checks on branches so we really only have the possibility of executing off the end of the length, and therefore cannot become unrepresentable.
This includes renaming Fifo.bsv to Fifos.bsv to account for a case insensitive file system which confuses this library with FIFO.bsv.
Also this includes an update of the verilator flags that are needed for modern verilator.
Finally, some verilator flag changes for building with LLVM.
Two of these were not properly restricted as read-only from CSRRX instructions,
and there was a bug in the WARL function for writing MIP,
and there was a bug in the TV-reporting of MIP updates.
When a CSRRx instruction writes to FCSR/FFLAGS/FRM, the CPU also
changes MSTATUS.FS and, by implication, MSTATUS.SD because the
floating point state has become "dirty". Tandem Verification
trace-generation was not reporting this update.
PLIC: updated to latest version from Piccolo/Flute.
MMIO_AXI4_Adapter: added workaround for Xilinx IP problem on 64-bit
AXI4 fabrics. Writes that specify 8-byte size, but only write in
upper or lower word using strobes, are converted into 4-byte size.
Core.bsv: added a notification to the Debug Module re. CPU halt.
MIP/MIE/SIP/SIE fields are WARL (Write-Any/Read-Legal). The CSR
register forces the user-privilege bits ([8,4,0]) to 0 since riscy-ooo
does not support user-level interrupts. However, function
Csrfile.fv_warl_xform() was not mirroring this correctly.
(1) riscy-ooo was mapping all unimplemented CSRs to a benign, user-privilege read-write CSR
Instead, we now catch this RenameStage and steer it to a trap.
(2) MSTATUS.FS was initialized to 2'b00 (absent/off); should be 2'b01 (present and initial)
Previously, the request went out into the fabric, and we were relying
on the fabric returning an error response. Some fabrics don't do this
reliably, so this removes that reliance on the fabric.
