Cheri-research/cheri-cap-lib
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added delta value field

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This commit is contained in:
Akilan Selvacoumar
2026-02-17 13:49:05 +00:00
parent 27e63bd9fd
commit dc9fc2bd7d
64 changed files with 4754 additions and 36 deletions
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CHERICC_Fat.bsv
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@@ -40,6 +40,8 @@ export CapPipe;
export CapFat; export CapFat;
export MW; export MW;
export OTypeW; export OTypeW;
export Delta;
export setDeltaValue;
export FlagsW; export FlagsW;
export Perms; export Perms;
export ResW; export ResW;
@@ -59,8 +61,8 @@ export Exp;
export MetaInfo; export MetaInfo;
export SetBoundsReturn; export SetBoundsReturn;
export CapTrim; export CapTrim;
export trimCap; // export trimCap;
export untrimCap; // export untrimCap;
// =============================================================================== // ===============================================================================
@@ -82,17 +84,20 @@ typedef 0 UPermW;
typedef 8 MW; typedef 8 MW;
typedef 6 ExpW; typedef 6 ExpW;
typedef 4 OTypeW; typedef 4 OTypeW;
typedef 24 Delta;
typedef `FLAGSW FlagsW; typedef `FLAGSW FlagsW;
typedef 32 CapAddrW; typedef 32 CapAddrW;
typedef 64 CapW; typedef 88 CapW;
`else // CAP128 is default `else // CAP128 is default
typedef 4 UPermW; typedef 4 UPermW;
typedef 14 MW; typedef 14 MW;
typedef 6 ExpW; typedef 6 ExpW;
typedef 18 OTypeW; typedef 18 OTypeW;
typedef 44 Delta;
typedef `FLAGSW FlagsW; typedef `FLAGSW FlagsW;
typedef 64 CapAddrW; typedef 64 CapAddrW;
typedef 128 CapW; // The capability width changes
typedef 172 CapW;
`endif `endif
// The Address type is used to represent the full sized address returned to the // The Address type is used to represent the full sized address returned to the
@@ -137,8 +142,9 @@ typedef SizeOf#(Perms) PermsW;
// The reserved bits // The reserved bits
typedef TSub#(CapW, TAdd#( CapAddrW typedef TSub#(CapW, TAdd#( CapAddrW
, TAdd#( OTypeW , TAdd#( OTypeW
, TAdd#( CBoundsW , TAdd#( Delta
, TAdd#(PermsW, FlagsW))))) ResW; , TAdd#( CBoundsW
, TAdd#(PermsW, FlagsW)))))) ResW;
// The full capability structure, including the "tag" bit. // The full capability structure, including the "tag" bit.
typedef struct { typedef struct {
Bool isCapability; Bool isCapability;
@@ -146,6 +152,7 @@ typedef struct {
Bit#(ResW) reserved; Bit#(ResW) reserved;
Bit#(FlagsW) flags; Bit#(FlagsW) flags;
Bit#(OTypeW) otype; Bit#(OTypeW) otype;
Bit#(Delta) delta;
CBounds bounds; CBounds bounds;
CapAddr address; CapAddr address;
} CapabilityInMemory deriving (Bits, Eq, FShow); // CapW + 1 (tag bit) } CapabilityInMemory deriving (Bits, Eq, FShow); // CapW + 1 (tag bit)
@@ -181,6 +188,7 @@ typedef struct {
Bit#(FlagsW) flags; Bit#(FlagsW) flags;
Bit#(ResW) reserved; Bit#(ResW) reserved;
Bit#(OTypeW) otype; Bit#(OTypeW) otype;
Bit#(Delta) delta;
Format format; Format format;
Bounds bounds; Bounds bounds;
} CapFat deriving (Bits); } CapFat deriving (Bits);
@@ -227,6 +235,7 @@ function CapFat unpackCap(Capability thin);
fat.flags = memCap.flags; fat.flags = memCap.flags;
fat.reserved = memCap.reserved; fat.reserved = memCap.reserved;
fat.otype = memCap.otype; fat.otype = memCap.otype;
fat.delta = memCap.delta;
match {.f, .b} = decBounds(memCap.bounds); match {.f, .b} = decBounds(memCap.bounds);
fat.format = f; fat.format = f;
fat.bounds = b; fat.bounds = b;
@@ -686,6 +695,13 @@ function CapFat unseal(CapFat cap, x _);
ret.otype = otype_unsealed; ret.otype = otype_unsealed;
return ret; return ret;
endfunction endfunction
// TODOD Creating Cap function to all delta value
// function CapFat addDelta(CapFat cap, x _);
// CapFat ret = cap;
// ret.delta = x;
// return ret;
// endfunction
function VnD#(CapFat) incOffsetFat( CapFat cap function VnD#(CapFat) incOffsetFat( CapFat cap
, CapAddr pointer , CapAddr pointer
, CapAddr offset // this is the increment in inc offset, and the offset in set offset , CapAddr offset // this is the increment in inc offset, and the offset in set offset
@@ -1033,7 +1049,7 @@ typedef struct {
// Note: commented out methods have a provided default implementation in the // Note: commented out methods have a provided default implementation in the
// CHERICap typeclass definition // CHERICap typeclass definition
instance CHERICap #(CapMem, OTypeW, FlagsW, CapAddrW, CapW, TSub #(MW, 3)); instance CHERICap #(CapMem, OTypeW, FlagsW, CapAddrW, CapW, TSub #(MW, 3), Delta);
// capability validity // capability validity
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
@@ -1101,6 +1117,7 @@ instance CHERICap #(CapMem, OTypeW, FlagsW, CapAddrW, CapW, TSub #(MW, 3));
, pack (cap.reserved) , pack (cap.reserved)
, pack (cap.flags) , pack (cap.flags)
, pack (cap.otype) , pack (cap.otype)
, pack (cap.delta)
, pack (cap.bounds) }; , pack (cap.bounds) };
endfunction endfunction
function getAddr (capMem); function getAddr (capMem);
@@ -1191,7 +1208,7 @@ endinstance
// Note: commented out methods have a provided default implementation in the // Note: commented out methods have a provided default implementation in the
// CHERICap typeclass definition // CHERICap typeclass definition
instance CHERICap #(CapReg, OTypeW, FlagsW, CapAddrW, CapW, TSub #(MW, 3)); instance CHERICap #(CapReg, OTypeW, FlagsW, CapAddrW, CapW, TSub #(MW, 3), Delta);
// capability validity // capability validity
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
@@ -1339,7 +1356,7 @@ instance CHERICap #(CapReg, OTypeW, FlagsW, CapAddrW, CapW, TSub #(MW, 3));
endinstance endinstance
instance CHERICap #(CapPipe, OTypeW, FlagsW, CapAddrW, CapW, TSub#(MW, 3)); instance CHERICap #(CapPipe, OTypeW, FlagsW, CapAddrW, CapW, TSub#(MW, 3), Delta);
//Functions supported by CapReg are just passed through //Functions supported by CapReg are just passed through
@@ -1387,6 +1404,15 @@ instance CHERICap #(CapPipe, OTypeW, FlagsW, CapAddrW, CapW, TSub#(MW, 3));
, mask: result.mask }; , mask: result.mask };
endfunction endfunction
// Create function to set delta value
function setDeltaValue (CapPipe cap, Bit#(Delta) delta);
// let result = setDelta(cap.capFat, delta);
cap.capFat.delta = delta;
return cap;
endfunction
function nullWithAddr (addr); function nullWithAddr (addr);
CapReg res = nullWithAddr(addr); CapReg res = nullWithAddr(addr);
return CapPipe { capFat: res, tempFields: getTempFields(res) }; return CapPipe { capFat: res, tempFields: getTempFields(res) };
@@ -1509,33 +1535,36 @@ typedef 48 VA_Width;
typedef struct { typedef struct {
Perms perms; Perms perms;
Bit#(FlagsW) flags; Bit#(FlagsW) flags;
Bit#(Delta) delta;
CBounds bounds; CBounds bounds;
Bit#(VA_Width) address; Bit#(VA_Width) address;
Bool validAddress; Bool validAddress;
} CapTrim deriving(Bits, Eq, FShow); } CapTrim deriving(Bits, Eq, FShow);
function CapTrim trimCap(CapMem cm); // function CapTrim trimCap(CapMem cm);
CapabilityInMemory cap = unpack(cm); // CapabilityInMemory cap = unpack(cm);
Bit#(TSub#(CapAddrW,VA_Width)) addr_upper = truncateLSB(cap.address); // Bit#(TSub#(CapAddrW,VA_Width)) addr_upper = truncateLSB(cap.address);
return CapTrim{perms: cap.perms, // return CapTrim{perms: cap.perms,
flags: cap.flags, // flags: cap.flags,
bounds: cap.bounds, // delta: cap.delta,
address: truncate(cap.address), // bounds: cap.bounds,
validAddress: (addr_upper==signExtend(cap.address[valueOf(VA_Width)-1])) // address: truncate(cap.address),
}; // validAddress: (addr_upper==signExtend(cap.address[valueOf(VA_Width)-1]))
endfunction // };
function CapMem untrimCap(CapTrim ct); // endfunction
// Encode an invalid address as the bit above the last valid bit being different. // function CapMem untrimCap(CapTrim ct);
Bit#(1) addressMsb = ct.address[valueOf(VA_Width)-1]; // // Encode an invalid address as the bit above the last valid bit being different.
if (!ct.validAddress) addressMsb = ^addressMsb; // Bit#(1) addressMsb = ct.address[valueOf(VA_Width)-1];
return pack(CapabilityInMemory{ // if (!ct.validAddress) addressMsb = ^addressMsb;
isCapability: True, // return pack(CapabilityInMemory{
perms: ct.perms, // isCapability: True,
reserved: 0, // perms: ct.perms,
flags: ct.flags, // reserved: 0,
otype: otype_unsealed, // flags: ct.flags,
bounds: ct.bounds, // otype: otype_unsealed,
address: signExtend({addressMsb,ct.address}) // delta: ct.delta,
}); // bounds: ct.bounds,
endfunction // address: signExtend({addressMsb,ct.address})
// });
// endfunction
endpackage endpackage

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@@ -119,7 +119,7 @@ endfunction
// XXX TODO augment with all architectural bounds/ repbounds ? // XXX TODO augment with all architectural bounds/ repbounds ?
function Fmt showCHERICap (capT cap) function Fmt showCHERICap (capT cap)
provisos (CHERICap #(capT , otypeW, flgW, addrW, inMemW, maskableW)); provisos (CHERICap #(capT , otypeW, flgW, addrW, inMemW, maskableW, delta));
return $format( "Valid: 0x%0x", isValidCap(cap)) + return $format( "Valid: 0x%0x", isValidCap(cap)) +
$format(" Perms: 0x%0x", getPerms(cap)) + $format(" Perms: 0x%0x", getPerms(cap)) +
$format(" Kind: ", fshow(getKind(cap))) + $format(" Kind: ", fshow(getKind(cap))) +
@@ -153,8 +153,9 @@ typeclass CHERICap #( type capT // type of the CHERICap capability
, numeric type addrW // width of the address , numeric type addrW // width of the address
, numeric type inMemW // width of the capability in mem , numeric type inMemW // width of the capability in mem
, numeric type maskableW // width of maskable bits , numeric type maskableW // width of maskable bits
, numeric type delta // size of delta (tlb bypass)
) )
dependencies (capT determines (otypeW, flgW, addrW, inMemW, maskableW)); dependencies (capT determines (otypeW, flgW, addrW, inMemW, maskableW, delta));
// capability validity // capability validity
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
@@ -320,6 +321,9 @@ typeclass CHERICap #( type capT // type of the CHERICap capability
// the null capability (requires a dummy proxy) // the null capability (requires a dummy proxy)
function capT nullCapFromDummy (capT dummy); function capT nullCapFromDummy (capT dummy);
// define set delta function
function capT setDeltaValue (capT cap, Bit #(delta) length);
// Assert that the encoding is valid // Assert that the encoding is valid
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////

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2
Makefile
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@@ -1,4 +1,4 @@
CAP ?= 64 CAP ?= 128
ifeq ($(CAP), 128) ifeq ($(CAP), 128)
BSCFLAGS = -D CAP128 BSCFLAGS = -D CAP128
else else

38
module_wrap128_almightyCap.v Normal file
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@@ -0,0 +1,38 @@
//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_almightyCap O 115 const
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_almightyCap(wrap128_almightyCap);
// value method wrap128_almightyCap
output [114 : 0] wrap128_almightyCap;
// signals for module outputs
wire [114 : 0] wrap128_almightyCap;
// value method wrap128_almightyCap
assign wrap128_almightyCap = 115'h40000000003FFDF555555690003F0 ;
endmodule // module_wrap128_almightyCap

115
module_wrap128_fromMem.v Normal file
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@@ -0,0 +1,115 @@
//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_fromMem O 115
// wrap128_fromMem_mem_cap I 89
//
// Combinational paths from inputs to outputs:
// wrap128_fromMem_mem_cap -> wrap128_fromMem
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_fromMem(wrap128_fromMem_mem_cap,
wrap128_fromMem);
// value method wrap128_fromMem
input [88 : 0] wrap128_fromMem_mem_cap;
output [114 : 0] wrap128_fromMem;
// signals for module outputs
wire [114 : 0] wrap128_fromMem;
// remaining internal signals
wire [88 : 0] thin__h113;
wire [31 : 0] x__h428;
wire [21 : 0] IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d33;
wire [7 : 0] bounds_topBits__h585,
res_addrBits__h131,
x__h618,
x__h638,
x__h653;
wire [5 : 0] x__h462;
wire [4 : 0] IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d52;
wire [2 : 0] repBound__h698, tb__h695;
wire [1 : 0] carry_out__h553,
impliedTopBits__h555,
len_correction__h554,
x__h635;
wire IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d39,
IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d40,
IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d42;
// value method wrap128_fromMem
assign wrap128_fromMem =
{ thin__h113[88],
thin__h113[31:0],
res_addrBits__h131,
thin__h113[87:46],
IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d33,
repBound__h698,
IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d39,
IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d40,
IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d52 } ;
// remaining internal signals
assign IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d33 =
{ thin__h113[46] ? x__h462 : 6'd0, x__h618, x__h638 } ;
assign IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d39 =
tb__h695 < repBound__h698 ;
assign IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d40 =
x__h638[7:5] < repBound__h698 ;
assign IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d42 =
res_addrBits__h131[7:5] < repBound__h698 ;
assign IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d52 =
{ IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d42,
(IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d39 ==
IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d42) ?
2'd0 :
((IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d39 &&
!IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d42) ?
2'd1 :
2'd3),
(IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d40 ==
IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d42) ?
2'd0 :
((IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d40 &&
!IF_wrap128_fromMem_mem_cap_XOR_15_CONCAT_DONTC_ETC___d42) ?
2'd1 :
2'd3) } ;
assign bounds_topBits__h585 = { 2'h2, thin__h113[45:43], 3'd0 } ;
assign carry_out__h553 = (x__h653[5:0] < x__h638[5:0]) ? 2'b01 : 2'b0 ;
assign impliedTopBits__h555 = x__h635 + len_correction__h554 ;
assign len_correction__h554 = thin__h113[46] ? 2'b01 : 2'b0 ;
assign repBound__h698 = x__h638[7:5] - 3'b001 ;
assign res_addrBits__h131 =
thin__h113[46] ? x__h428[7:0] : thin__h113[7:0] ;
assign tb__h695 = { impliedTopBits__h555, x__h653[5] } ;
assign thin__h113 = wrap128_fromMem_mem_cap ^ 89'h00007D55555430200000000 ;
assign x__h428 = thin__h113[31:0] >> x__h462 ;
assign x__h462 = { thin__h113[42:40], thin__h113[34:32] } ;
assign x__h618 = { impliedTopBits__h555, x__h653[5:0] } ;
assign x__h635 = x__h638[7:6] + carry_out__h553 ;
assign x__h638 =
thin__h113[46] ?
{ thin__h113[39:35], 3'd0 } :
thin__h113[39:32] ;
assign x__h653 = thin__h113[46] ? bounds_topBits__h585 : thin__h113[47:40] ;
endmodule // module_wrap128_fromMem

42
module_wrap128_getAddr.v Normal file
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@@ -0,0 +1,42 @@
//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_getAddr O 32
// wrap128_getAddr_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap128_getAddr_cap -> wrap128_getAddr
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_getAddr(wrap128_getAddr_cap,
wrap128_getAddr);
// value method wrap128_getAddr
input [114 : 0] wrap128_getAddr_cap;
output [31 : 0] wrap128_getAddr;
// signals for module outputs
wire [31 : 0] wrap128_getAddr;
// value method wrap128_getAddr
assign wrap128_getAddr = wrap128_getAddr_cap[113:82] ;
endmodule // module_wrap128_getAddr

55
module_wrap128_getBase.v Normal file
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@@ -0,0 +1,55 @@
//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_getBase O 32
// wrap128_getBase_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap128_getBase_cap -> wrap128_getBase
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_getBase(wrap128_getBase_cap,
wrap128_getBase);
// value method wrap128_getBase
input [114 : 0] wrap128_getBase_cap;
output [31 : 0] wrap128_getBase;
// signals for module outputs
wire [31 : 0] wrap128_getBase;
// remaining internal signals
wire [31 : 0] addBase__h64;
wire [23 : 0] mask__h65;
wire [9 : 0] x__h167;
// value method wrap128_getBase
assign wrap128_getBase =
{ wrap128_getBase_cap[113:90] & mask__h65, 8'd0 } +
addBase__h64 ;
// remaining internal signals
assign addBase__h64 =
{ {22{x__h167[9]}}, x__h167 } << wrap128_getBase_cap[31:26] ;
assign mask__h65 = 24'd16777215 << wrap128_getBase_cap[31:26] ;
assign x__h167 = { wrap128_getBase_cap[1:0], wrap128_getBase_cap[17:10] } ;
endmodule // module_wrap128_getBase

42
module_wrap128_getFlags.v Normal file
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@@ -0,0 +1,42 @@
//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_getFlags O 1
// wrap128_getFlags_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap128_getFlags_cap -> wrap128_getFlags
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_getFlags(wrap128_getFlags_cap,
wrap128_getFlags);
// value method wrap128_getFlags
input [114 : 0] wrap128_getFlags_cap;
output wrap128_getFlags;
// signals for module outputs
wire wrap128_getFlags;
// value method wrap128_getFlags
assign wrap128_getFlags = wrap128_getFlags_cap[61] ;
endmodule // module_wrap128_getFlags

42
module_wrap128_getHardPerms.v Normal file
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@@ -0,0 +1,42 @@
//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_getHardPerms O 12
// wrap128_getHardPerms_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap128_getHardPerms_cap -> wrap128_getHardPerms
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_getHardPerms(wrap128_getHardPerms_cap,
wrap128_getHardPerms);
// value method wrap128_getHardPerms
input [114 : 0] wrap128_getHardPerms_cap;
output [11 : 0] wrap128_getHardPerms;
// signals for module outputs
wire [11 : 0] wrap128_getHardPerms;
// value method wrap128_getHardPerms
assign wrap128_getHardPerms = wrap128_getHardPerms_cap[73:62] ;
endmodule // module_wrap128_getHardPerms

59
module_wrap128_getKind.v Normal file
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@@ -0,0 +1,59 @@
//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_getKind O 7
// wrap128_getKind_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap128_getKind_cap -> wrap128_getKind
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_getKind(wrap128_getKind_cap,
wrap128_getKind);
// value method wrap128_getKind
input [114 : 0] wrap128_getKind_cap;
output [6 : 0] wrap128_getKind;
// signals for module outputs
wire [6 : 0] wrap128_getKind;
// remaining internal signals
reg [2 : 0] CASE_wrap128_getKind_cap_BITS_60_TO_57_12_3_13_ETC__q1;
// value method wrap128_getKind
assign wrap128_getKind =
{ CASE_wrap128_getKind_cap_BITS_60_TO_57_12_3_13_ETC__q1,
wrap128_getKind_cap[60:57] } ;
// remaining internal signals
always@(wrap128_getKind_cap)
begin
case (wrap128_getKind_cap[60:57])
4'd12: CASE_wrap128_getKind_cap_BITS_60_TO_57_12_3_13_ETC__q1 = 3'd3;
4'd13: CASE_wrap128_getKind_cap_BITS_60_TO_57_12_3_13_ETC__q1 = 3'd2;
4'd14: CASE_wrap128_getKind_cap_BITS_60_TO_57_12_3_13_ETC__q1 = 3'd1;
4'd15: CASE_wrap128_getKind_cap_BITS_60_TO_57_12_3_13_ETC__q1 = 3'd0;
default: CASE_wrap128_getKind_cap_BITS_60_TO_57_12_3_13_ETC__q1 = 3'd4;
endcase
end
endmodule // module_wrap128_getKind

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_getLength O 33
// wrap128_getLength_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap128_getLength_cap -> wrap128_getLength
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_getLength(wrap128_getLength_cap,
wrap128_getLength);
// value method wrap128_getLength
input [114 : 0] wrap128_getLength_cap;
output [32 : 0] wrap128_getLength;
// signals for module outputs
wire [32 : 0] wrap128_getLength;
// remaining internal signals
wire [32 : 0] length__h66;
wire [9 : 0] base__h65, top__h64, x__h125;
// value method wrap128_getLength
assign wrap128_getLength =
(wrap128_getLength_cap[31:26] < 6'd26) ?
length__h66 :
33'h1FFFFFFFF ;
// remaining internal signals
assign base__h65 =
{ wrap128_getLength_cap[1:0], wrap128_getLength_cap[17:10] } ;
assign length__h66 = { 23'd0, x__h125 } << wrap128_getLength_cap[31:26] ;
assign top__h64 =
{ wrap128_getLength_cap[3:2], wrap128_getLength_cap[25:18] } ;
assign x__h125 = top__h64 - base__h65 ;
endmodule // module_wrap128_getLength

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_getOffset O 32
// wrap128_getOffset_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap128_getOffset_cap -> wrap128_getOffset
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_getOffset(wrap128_getOffset_cap,
wrap128_getOffset);
// value method wrap128_getOffset
input [114 : 0] wrap128_getOffset_cap;
output [31 : 0] wrap128_getOffset;
// signals for module outputs
wire [31 : 0] wrap128_getOffset;
// remaining internal signals
wire [31 : 0] addrLSB__h68, x__h204, x__h79, x__h81, y__h203;
wire [9 : 0] base__h66, offset__h67;
// value method wrap128_getOffset
assign wrap128_getOffset = x__h79 | addrLSB__h68 ;
// remaining internal signals
assign addrLSB__h68 = wrap128_getOffset_cap[113:82] & y__h203 ;
assign base__h66 =
{ wrap128_getOffset_cap[1:0], wrap128_getOffset_cap[17:10] } ;
assign offset__h67 = { 2'b0, wrap128_getOffset_cap[81:74] } - base__h66 ;
assign x__h204 = 32'hFFFFFFFF << wrap128_getOffset_cap[31:26] ;
assign x__h79 = x__h81 << wrap128_getOffset_cap[31:26] ;
assign x__h81 = { {22{offset__h67[9]}}, offset__h67 } ;
assign y__h203 = ~x__h204 ;
endmodule // module_wrap128_getOffset

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_getPerms O 31
// wrap128_getPerms_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap128_getPerms_cap -> wrap128_getPerms
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_getPerms(wrap128_getPerms_cap,
wrap128_getPerms);
// value method wrap128_getPerms
input [114 : 0] wrap128_getPerms_cap;
output [30 : 0] wrap128_getPerms;
// signals for module outputs
wire [30 : 0] wrap128_getPerms;
// value method wrap128_getPerms
assign wrap128_getPerms = { 19'd0, wrap128_getPerms_cap[73:62] } ;
endmodule // module_wrap128_getPerms

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_getSoftPerms O 16 const
// wrap128_getSoftPerms_cap I 115 unused
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_getSoftPerms(wrap128_getSoftPerms_cap,
wrap128_getSoftPerms);
// value method wrap128_getSoftPerms
input [114 : 0] wrap128_getSoftPerms_cap;
output [15 : 0] wrap128_getSoftPerms;
// signals for module outputs
wire [15 : 0] wrap128_getSoftPerms;
// value method wrap128_getSoftPerms
assign wrap128_getSoftPerms = 16'd0 ;
endmodule // module_wrap128_getSoftPerms

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_getTop O 33
// wrap128_getTop_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap128_getTop_cap -> wrap128_getTop
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_getTop(wrap128_getTop_cap,
wrap128_getTop);
// value method wrap128_getTop
input [114 : 0] wrap128_getTop_cap;
output [32 : 0] wrap128_getTop;
// signals for module outputs
wire [32 : 0] wrap128_getTop;
// remaining internal signals
wire [32 : 0] addTop__h64, result__h512, ret__h66;
wire [24 : 0] mask__h65;
wire [23 : 0] wrap128_getTop_cap_BITS_113_TO_90_PLUS_SEXT_wr_ETC__q2;
wire [9 : 0] x__h178;
wire [1 : 0] wrap128_getTop_cap_BITS_1_TO_0__q1;
// value method wrap128_getTop
assign wrap128_getTop =
(wrap128_getTop_cap[31:26] < 6'd25 &&
ret__h66[32:31] -
{ 1'b0,
(wrap128_getTop_cap[31:26] == 6'd24) ?
wrap128_getTop_cap[17] :
wrap128_getTop_cap_BITS_113_TO_90_PLUS_SEXT_wr_ETC__q2[23] } >
2'd1) ?
result__h512 :
ret__h66 ;
// remaining internal signals
assign addTop__h64 =
{ {23{x__h178[9]}}, x__h178 } << wrap128_getTop_cap[31:26] ;
assign mask__h65 = 25'd33554431 << wrap128_getTop_cap[31:26] ;
assign result__h512 = { ~ret__h66[32], ret__h66[31:0] } ;
assign ret__h66 =
{ { 1'b0, wrap128_getTop_cap[113:90] } & mask__h65, 8'd0 } +
addTop__h64 ;
assign wrap128_getTop_cap_BITS_113_TO_90_PLUS_SEXT_wr_ETC__q2 =
wrap128_getTop_cap[113:90] +
({ {22{wrap128_getTop_cap_BITS_1_TO_0__q1[1]}},
wrap128_getTop_cap_BITS_1_TO_0__q1 } <<
wrap128_getTop_cap[31:26]) ;
assign wrap128_getTop_cap_BITS_1_TO_0__q1 = wrap128_getTop_cap[1:0] ;
assign x__h178 = { wrap128_getTop_cap[3:2], wrap128_getTop_cap[25:18] } ;
endmodule // module_wrap128_getTop

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_incOffset O 116
// wrap128_incOffset_cap I 115
// wrap128_incOffset_inc I 32
//
// Combinational paths from inputs to outputs:
// (wrap128_incOffset_cap, wrap128_incOffset_inc) -> wrap128_incOffset
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_incOffset(wrap128_incOffset_cap,
wrap128_incOffset_inc,
wrap128_incOffset);
// value method wrap128_incOffset
input [114 : 0] wrap128_incOffset_cap;
input [31 : 0] wrap128_incOffset_inc;
output [115 : 0] wrap128_incOffset;
// signals for module outputs
wire [115 : 0] wrap128_incOffset;
// remaining internal signals
wire [31 : 0] result_d_address__h574, x__h488, x__h597;
wire [23 : 0] highBitsfilter__h79,
highOffsetBits__h80,
signBits__h77,
x__h107;
wire [7 : 0] repBoundBits__h86, toBoundsM1__h90, toBounds__h89;
wire [3 : 0] IF_wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d53;
wire [2 : 0] repBound__h738;
wire IF_wrap128_incOffset_inc_BIT_31_THEN_NOT_wrap1_ETC___d23,
wrap128_incOffset_cap_BITS_113_TO_82_0_PLUS_wr_ETC___d43,
wrap128_incOffset_cap_BITS_17_TO_15_7_ULT_wrap_ETC___d41,
wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_wrap_ETC___d40;
// value method wrap128_incOffset
assign wrap128_incOffset =
{ highOffsetBits__h80 == 24'd0 &&
IF_wrap128_incOffset_inc_BIT_31_THEN_NOT_wrap1_ETC___d23 ||
wrap128_incOffset_cap[31:26] >= 6'd24,
(highOffsetBits__h80 == 24'd0 &&
IF_wrap128_incOffset_inc_BIT_31_THEN_NOT_wrap1_ETC___d23 ||
wrap128_incOffset_cap[31:26] >= 6'd24) &&
wrap128_incOffset_cap[114],
result_d_address__h574,
x__h597[7:0],
wrap128_incOffset_cap[73:10],
repBound__h738,
wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_wrap_ETC___d40,
wrap128_incOffset_cap_BITS_17_TO_15_7_ULT_wrap_ETC___d41,
wrap128_incOffset_cap_BITS_113_TO_82_0_PLUS_wr_ETC___d43,
IF_wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d53 } ;
// remaining internal signals
assign IF_wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d53 =
{ (wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_wrap_ETC___d40 ==
wrap128_incOffset_cap_BITS_113_TO_82_0_PLUS_wr_ETC___d43) ?
2'd0 :
((wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_wrap_ETC___d40 &&
!wrap128_incOffset_cap_BITS_113_TO_82_0_PLUS_wr_ETC___d43) ?
2'd1 :
2'd3),
(wrap128_incOffset_cap_BITS_17_TO_15_7_ULT_wrap_ETC___d41 ==
wrap128_incOffset_cap_BITS_113_TO_82_0_PLUS_wr_ETC___d43) ?
2'd0 :
((wrap128_incOffset_cap_BITS_17_TO_15_7_ULT_wrap_ETC___d41 &&
!wrap128_incOffset_cap_BITS_113_TO_82_0_PLUS_wr_ETC___d43) ?
2'd1 :
2'd3) } ;
assign IF_wrap128_incOffset_inc_BIT_31_THEN_NOT_wrap1_ETC___d23 =
wrap128_incOffset_inc[31] ?
x__h488[7:0] >= toBounds__h89 &&
repBoundBits__h86 != wrap128_incOffset_cap[81:74] :
x__h488[7:0] < toBoundsM1__h90 ;
assign highBitsfilter__h79 = 24'd16777215 << wrap128_incOffset_cap[31:26] ;
assign highOffsetBits__h80 = x__h107 & highBitsfilter__h79 ;
assign repBoundBits__h86 = { wrap128_incOffset_cap[9:7], 5'd0 } ;
assign repBound__h738 = wrap128_incOffset_cap[17:15] - 3'b001 ;
assign result_d_address__h574 =
wrap128_incOffset_cap[113:82] + wrap128_incOffset_inc ;
assign signBits__h77 = {24{wrap128_incOffset_inc[31]}} ;
assign toBoundsM1__h90 = repBoundBits__h86 + ~wrap128_incOffset_cap[81:74] ;
assign toBounds__h89 = repBoundBits__h86 - wrap128_incOffset_cap[81:74] ;
assign wrap128_incOffset_cap_BITS_113_TO_82_0_PLUS_wr_ETC___d43 =
x__h597[7:5] < repBound__h738 ;
assign wrap128_incOffset_cap_BITS_17_TO_15_7_ULT_wrap_ETC___d41 =
wrap128_incOffset_cap[17:15] < repBound__h738 ;
assign wrap128_incOffset_cap_BITS_25_TO_23_9_ULT_wrap_ETC___d40 =
wrap128_incOffset_cap[25:23] < repBound__h738 ;
assign x__h107 = wrap128_incOffset_inc[31:8] ^ signBits__h77 ;
assign x__h488 = wrap128_incOffset_inc >> wrap128_incOffset_cap[31:26] ;
assign x__h597 = result_d_address__h574 >> wrap128_incOffset_cap[31:26] ;
endmodule // module_wrap128_incOffset

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_isInBounds O 1
// wrap128_isInBounds_cap I 115
// wrap128_isInBounds_isTopIncluded I 1
//
// Combinational paths from inputs to outputs:
// (wrap128_isInBounds_cap,
// wrap128_isInBounds_isTopIncluded) -> wrap128_isInBounds
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_isInBounds(wrap128_isInBounds_cap,
wrap128_isInBounds_isTopIncluded,
wrap128_isInBounds);
// value method wrap128_isInBounds
input [114 : 0] wrap128_isInBounds_cap;
input wrap128_isInBounds_isTopIncluded;
output wrap128_isInBounds;
// signals for module outputs
wire wrap128_isInBounds;
// value method wrap128_isInBounds
assign wrap128_isInBounds =
((wrap128_isInBounds_cap[6] == wrap128_isInBounds_cap[4]) ?
(wrap128_isInBounds_isTopIncluded ?
wrap128_isInBounds_cap[81:74] <=
wrap128_isInBounds_cap[25:18] :
wrap128_isInBounds_cap[81:74] <
wrap128_isInBounds_cap[25:18]) :
wrap128_isInBounds_cap[6]) &&
((wrap128_isInBounds_cap[5] == wrap128_isInBounds_cap[4]) ?
wrap128_isInBounds_cap[81:74] >=
wrap128_isInBounds_cap[17:10] :
wrap128_isInBounds_cap[4]) ;
endmodule // module_wrap128_isInBounds

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_isValidCap O 1
// wrap128_isValidCap_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap128_isValidCap_cap -> wrap128_isValidCap
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_isValidCap(wrap128_isValidCap_cap,
wrap128_isValidCap);
// value method wrap128_isValidCap
input [114 : 0] wrap128_isValidCap_cap;
output wrap128_isValidCap;
// signals for module outputs
wire wrap128_isValidCap;
// value method wrap128_isValidCap
assign wrap128_isValidCap = wrap128_isValidCap_cap[114] ;
endmodule // module_wrap128_isValidCap

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_modifyOffset O 116
// wrap128_modifyOffset_cap I 115
// wrap128_modifyOffset_offset I 32
// wrap128_modifyOffset_doInc I 1
//
// Combinational paths from inputs to outputs:
// (wrap128_modifyOffset_cap,
// wrap128_modifyOffset_offset,
// wrap128_modifyOffset_doInc) -> wrap128_modifyOffset
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_modifyOffset(wrap128_modifyOffset_cap,
wrap128_modifyOffset_offset,
wrap128_modifyOffset_doInc,
wrap128_modifyOffset);
// value method wrap128_modifyOffset
input [114 : 0] wrap128_modifyOffset_cap;
input [31 : 0] wrap128_modifyOffset_offset;
input wrap128_modifyOffset_doInc;
output [115 : 0] wrap128_modifyOffset;
// signals for module outputs
wire [115 : 0] wrap128_modifyOffset;
// remaining internal signals
reg [1 : 0] mask__h585;
wire [31 : 0] addBase__h631,
pointer__h74,
result_d_address__h600,
ret___1_address__h611,
x__h491,
x__h741;
wire [23 : 0] highOffsetBits__h81, mask__h632, signBits__h78, x__h108;
wire [9 : 0] x__h682;
wire [7 : 0] newAddrBits__h584,
repBoundBits__h87,
result_d_addrBits__h601,
toBoundsM1_A__h86,
toBoundsM1_B__h89,
toBoundsM1__h91,
toBounds_A__h85,
toBounds_B__h88,
toBounds__h90;
wire [3 : 0] IF_wrap128_modifyOffset_cap_BITS_25_TO_23_9_UL_ETC___d83;
wire [2 : 0] repBound__h881;
wire IF_wrap128_modifyOffset_doInc_THEN_wrap128_mod_ETC___d73,
IF_wrap128_modifyOffset_offset_BIT_31_THEN_NOT_ETC___d34,
NOT_wrap128_modifyOffset_offset_SRL_wrap128_mo_ETC___d25,
wrap128_modifyOffset_cap_BITS_17_TO_15_7_ULT_w_ETC___d71,
wrap128_modifyOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d70;
// value method wrap128_modifyOffset
assign wrap128_modifyOffset =
{ highOffsetBits__h81 == 24'd0 &&
IF_wrap128_modifyOffset_offset_BIT_31_THEN_NOT_ETC___d34 ||
wrap128_modifyOffset_cap[31:26] >= 6'd24,
(highOffsetBits__h81 == 24'd0 &&
IF_wrap128_modifyOffset_offset_BIT_31_THEN_NOT_ETC___d34 ||
wrap128_modifyOffset_cap[31:26] >= 6'd24) &&
wrap128_modifyOffset_cap[114],
result_d_address__h600,
result_d_addrBits__h601,
wrap128_modifyOffset_cap[73:10],
repBound__h881,
wrap128_modifyOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d70,
wrap128_modifyOffset_cap_BITS_17_TO_15_7_ULT_w_ETC___d71,
IF_wrap128_modifyOffset_doInc_THEN_wrap128_mod_ETC___d73,
IF_wrap128_modifyOffset_cap_BITS_25_TO_23_9_UL_ETC___d83 } ;
// remaining internal signals
assign IF_wrap128_modifyOffset_cap_BITS_25_TO_23_9_UL_ETC___d83 =
{ (wrap128_modifyOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d70 ==
IF_wrap128_modifyOffset_doInc_THEN_wrap128_mod_ETC___d73) ?
2'd0 :
((wrap128_modifyOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d70 &&
!IF_wrap128_modifyOffset_doInc_THEN_wrap128_mod_ETC___d73) ?
2'd1 :
2'd3),
(wrap128_modifyOffset_cap_BITS_17_TO_15_7_ULT_w_ETC___d71 ==
IF_wrap128_modifyOffset_doInc_THEN_wrap128_mod_ETC___d73) ?
2'd0 :
((wrap128_modifyOffset_cap_BITS_17_TO_15_7_ULT_w_ETC___d71 &&
!IF_wrap128_modifyOffset_doInc_THEN_wrap128_mod_ETC___d73) ?
2'd1 :
2'd3) } ;
assign IF_wrap128_modifyOffset_doInc_THEN_wrap128_mod_ETC___d73 =
result_d_addrBits__h601[7:5] < repBound__h881 ;
assign IF_wrap128_modifyOffset_offset_BIT_31_THEN_NOT_ETC___d34 =
wrap128_modifyOffset_offset[31] ?
NOT_wrap128_modifyOffset_offset_SRL_wrap128_mo_ETC___d25 :
(wrap128_modifyOffset_doInc ?
x__h491[7:0] < toBoundsM1__h91 :
x__h491[7:0] <= toBoundsM1__h91) ;
assign NOT_wrap128_modifyOffset_offset_SRL_wrap128_mo_ETC___d25 =
x__h491[7:0] >= toBounds__h90 &&
(!wrap128_modifyOffset_doInc ||
repBoundBits__h87 != wrap128_modifyOffset_cap[81:74]) ;
assign addBase__h631 =
{ {22{x__h682[9]}}, x__h682 } <<
wrap128_modifyOffset_cap[31:26] ;
assign highOffsetBits__h81 = x__h108 & mask__h632 ;
assign mask__h632 = 24'd16777215 << wrap128_modifyOffset_cap[31:26] ;
assign newAddrBits__h584 = wrap128_modifyOffset_cap[17:10] + x__h491[7:0] ;
assign pointer__h74 =
wrap128_modifyOffset_cap[113:82] + wrap128_modifyOffset_offset ;
assign repBoundBits__h87 = { wrap128_modifyOffset_cap[9:7], 5'd0 } ;
assign repBound__h881 = wrap128_modifyOffset_cap[17:15] - 3'b001 ;
assign result_d_addrBits__h601 =
wrap128_modifyOffset_doInc ?
x__h741[7:0] :
{ mask__h585, 6'd63 } & newAddrBits__h584 ;
assign result_d_address__h600 =
wrap128_modifyOffset_doInc ?
pointer__h74 :
ret___1_address__h611 ;
assign ret___1_address__h611 =
{ wrap128_modifyOffset_cap[113:90] & mask__h632, 8'd0 } +
addBase__h631 +
wrap128_modifyOffset_offset ;
assign signBits__h78 = {24{wrap128_modifyOffset_offset[31]}} ;
assign toBoundsM1_A__h86 = { 3'b110, ~wrap128_modifyOffset_cap[14:10] } ;
assign toBoundsM1_B__h89 =
repBoundBits__h87 + ~wrap128_modifyOffset_cap[81:74] ;
assign toBoundsM1__h91 =
wrap128_modifyOffset_doInc ?
toBoundsM1_B__h89 :
toBoundsM1_A__h86 ;
assign toBounds_A__h85 =
8'd224 - { 3'b0, wrap128_modifyOffset_cap[14:10] } ;
assign toBounds_B__h88 =
repBoundBits__h87 - wrap128_modifyOffset_cap[81:74] ;
assign toBounds__h90 =
wrap128_modifyOffset_doInc ? toBounds_B__h88 : toBounds_A__h85 ;
assign wrap128_modifyOffset_cap_BITS_17_TO_15_7_ULT_w_ETC___d71 =
wrap128_modifyOffset_cap[17:15] < repBound__h881 ;
assign wrap128_modifyOffset_cap_BITS_25_TO_23_9_ULT_w_ETC___d70 =
wrap128_modifyOffset_cap[25:23] < repBound__h881 ;
assign x__h108 = wrap128_modifyOffset_offset[31:8] ^ signBits__h78 ;
assign x__h491 =
wrap128_modifyOffset_offset >> wrap128_modifyOffset_cap[31:26] ;
assign x__h682 =
{ wrap128_modifyOffset_cap[1:0],
wrap128_modifyOffset_cap[17:10] } ;
assign x__h741 = pointer__h74 >> wrap128_modifyOffset_cap[31:26] ;
always@(wrap128_modifyOffset_cap)
begin
case (wrap128_modifyOffset_cap[31:26])
6'd25: mask__h585 = 2'b01;
6'd26: mask__h585 = 2'b0;
default: mask__h585 = 2'b11;
endcase
end
endmodule // module_wrap128_modifyOffset

38
module_wrap128_nullCap.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_nullCap O 115 const
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_nullCap(wrap128_nullCap);
// value method wrap128_nullCap
output [114 : 0] wrap128_nullCap;
// signals for module outputs
wire [114 : 0] wrap128_nullCap;
// value method wrap128_nullCap
assign wrap128_nullCap = 115'h00000000000001F555555690003F0 ;
endmodule // module_wrap128_nullCap

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_nullWithAddr O 115
// wrap128_nullWithAddr_addr I 32
//
// Combinational paths from inputs to outputs:
// wrap128_nullWithAddr_addr -> wrap128_nullWithAddr
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_nullWithAddr(wrap128_nullWithAddr_addr,
wrap128_nullWithAddr);
// value method wrap128_nullWithAddr
input [31 : 0] wrap128_nullWithAddr_addr;
output [114 : 0] wrap128_nullWithAddr;
// signals for module outputs
wire [114 : 0] wrap128_nullWithAddr;
// remaining internal signals
wire [7 : 0] res_addrBits__h116;
// value method wrap128_nullWithAddr
assign wrap128_nullWithAddr =
{ 1'd0,
wrap128_nullWithAddr_addr,
res_addrBits__h116,
74'h0001F555555690003F0 } ;
// remaining internal signals
assign res_addrBits__h116 = { 2'd0, wrap128_nullWithAddr_addr[31:26] } ;
endmodule // module_wrap128_nullWithAddr

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_setAddr O 116
// wrap128_setAddr_cap I 115
// wrap128_setAddr_addr I 32
//
// Combinational paths from inputs to outputs:
// (wrap128_setAddr_cap, wrap128_setAddr_addr) -> wrap128_setAddr
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_setAddr(wrap128_setAddr_cap,
wrap128_setAddr_addr,
wrap128_setAddr);
// value method wrap128_setAddr
input [114 : 0] wrap128_setAddr_cap;
input [31 : 0] wrap128_setAddr_addr;
output [115 : 0] wrap128_setAddr;
// signals for module outputs
wire [115 : 0] wrap128_setAddr;
// remaining internal signals
wire [31 : 0] x__h102;
wire [23 : 0] deltaAddrHi__h76, deltaAddrUpper__h78, mask__h77;
wire [3 : 0] IF_wrap128_setAddr_cap_BITS_25_TO_23_7_ULT_wra_ETC___d40;
wire [2 : 0] repBound__h430;
wire [1 : 0] x__h84;
wire SEXT__0b0_CONCAT_wrap128_setAddr_addr_SRL_wrap_ETC___d18,
wrap128_setAddr_addr_SRL_wrap128_setAddr_cap_B_ETC___d30,
wrap128_setAddr_cap_BITS_17_TO_15_5_ULT_wrap12_ETC___d29,
wrap128_setAddr_cap_BITS_25_TO_23_7_ULT_wrap12_ETC___d28;
// value method wrap128_setAddr
assign wrap128_setAddr =
{ SEXT__0b0_CONCAT_wrap128_setAddr_addr_SRL_wrap_ETC___d18,
SEXT__0b0_CONCAT_wrap128_setAddr_addr_SRL_wrap_ETC___d18 &&
wrap128_setAddr_cap[114],
wrap128_setAddr_addr,
x__h102[7:0],
wrap128_setAddr_cap[73:10],
repBound__h430,
wrap128_setAddr_cap_BITS_25_TO_23_7_ULT_wrap12_ETC___d28,
wrap128_setAddr_cap_BITS_17_TO_15_5_ULT_wrap12_ETC___d29,
wrap128_setAddr_addr_SRL_wrap128_setAddr_cap_B_ETC___d30,
IF_wrap128_setAddr_cap_BITS_25_TO_23_7_ULT_wra_ETC___d40 } ;
// remaining internal signals
assign IF_wrap128_setAddr_cap_BITS_25_TO_23_7_ULT_wra_ETC___d40 =
{ (wrap128_setAddr_cap_BITS_25_TO_23_7_ULT_wrap12_ETC___d28 ==
wrap128_setAddr_addr_SRL_wrap128_setAddr_cap_B_ETC___d30) ?
2'd0 :
((wrap128_setAddr_cap_BITS_25_TO_23_7_ULT_wrap12_ETC___d28 &&
!wrap128_setAddr_addr_SRL_wrap128_setAddr_cap_B_ETC___d30) ?
2'd1 :
2'd3),
(wrap128_setAddr_cap_BITS_17_TO_15_5_ULT_wrap12_ETC___d29 ==
wrap128_setAddr_addr_SRL_wrap128_setAddr_cap_B_ETC___d30) ?
2'd0 :
((wrap128_setAddr_cap_BITS_17_TO_15_5_ULT_wrap12_ETC___d29 &&
!wrap128_setAddr_addr_SRL_wrap128_setAddr_cap_B_ETC___d30) ?
2'd1 :
2'd3) } ;
assign SEXT__0b0_CONCAT_wrap128_setAddr_addr_SRL_wrap_ETC___d18 =
deltaAddrHi__h76 == deltaAddrUpper__h78 ;
assign deltaAddrHi__h76 =
{ {22{x__h84[1]}}, x__h84 } << wrap128_setAddr_cap[31:26] ;
assign deltaAddrUpper__h78 =
(wrap128_setAddr_addr[31:8] & mask__h77) -
(wrap128_setAddr_cap[113:90] & mask__h77) ;
assign mask__h77 = 24'd16777215 << wrap128_setAddr_cap[31:26] ;
assign repBound__h430 = wrap128_setAddr_cap[17:15] - 3'b001 ;
assign wrap128_setAddr_addr_SRL_wrap128_setAddr_cap_B_ETC___d30 =
x__h102[7:5] < repBound__h430 ;
assign wrap128_setAddr_cap_BITS_17_TO_15_5_ULT_wrap12_ETC___d29 =
wrap128_setAddr_cap[17:15] < repBound__h430 ;
assign wrap128_setAddr_cap_BITS_25_TO_23_7_ULT_wrap12_ETC___d28 =
wrap128_setAddr_cap[25:23] < repBound__h430 ;
assign x__h102 = wrap128_setAddr_addr >> wrap128_setAddr_cap[31:26] ;
assign x__h84 =
{ 1'b0, x__h102[7:5] < wrap128_setAddr_cap[9:7] } -
{ 1'b0, wrap128_setAddr_cap[4] } ;
endmodule // module_wrap128_setAddr

561
module_wrap128_setBounds.v Normal file
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@@ -0,0 +1,561 @@
//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_setBounds O 116
// wrap128_setBounds_cap I 115
// wrap128_setBounds_length I 32
//
// Combinational paths from inputs to outputs:
// (wrap128_setBounds_cap, wrap128_setBounds_length) -> wrap128_setBounds
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_setBounds(wrap128_setBounds_cap,
wrap128_setBounds_length,
wrap128_setBounds);
// value method wrap128_setBounds
input [114 : 0] wrap128_setBounds_cap;
input [31 : 0] wrap128_setBounds_length;
output [115 : 0] wrap128_setBounds;
// signals for module outputs
wire [115 : 0] wrap128_setBounds;
// remaining internal signals
wire [33 : 0] base__h84,
len__h86,
lmaskLo__h92,
lmaskLor__h91,
mwLsbMask__h100,
top__h87,
x__h4494,
x__h4615,
x__h4798,
y__h4495;
wire [31 : 0] wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d110,
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d10,
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d13,
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d16,
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d4,
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d7;
wire [15 : 0] IF_NOT_wrap128_setBounds_length_BIT_31_1_2_AND_ETC___d212;
wire [8 : 0] x__h4837;
wire [7 : 0] _theResult_____3_fst_bounds_topBits__h4604,
result_cap_addrBits__h4434,
ret_bounds_baseBits__h4780,
ret_bounds_topBits__h4600,
ret_bounds_topBits__h4829,
x__h4874,
x__h4877;
wire [5 : 0] IF_wrap128_setBounds_length_AND_15_CONCAT_INV__ETC___d190,
_25_MINUS_0_CONCAT_IF_wrap128_setBounds_length__ETC___d183;
wire [3 : 0] IF_IF_NOT_wrap128_setBounds_length_BIT_31_1_2__ETC___d234;
wire [2 : 0] repBound__h4867;
wire IF_NOT_wrap128_setBounds_length_BIT_31_1_2_AND_ETC___d221,
IF_NOT_wrap128_setBounds_length_BIT_31_1_2_AND_ETC___d222,
IF_wrap128_setBounds_length_AND_15_CONCAT_INV__ETC___d224,
NOT_0_CONCAT_wrap128_setBounds_length_OR_0_CON_ETC___d122,
NOT_0b0_CONCAT_wrap128_setBounds_cap_BITS_113__ETC___d191,
NOT_0b0_CONCAT_wrap128_setBounds_cap_BITS_113__ETC___d202,
_0b0_CONCAT_wrap128_setBounds_cap_BITS_113_TO_8_ETC___d105,
wrap128_setBounds_cap_BITS_113_TO_82_AND_0_CON_ETC___d98,
wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d123,
wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d129,
wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d130;
// value method wrap128_setBounds
assign wrap128_setBounds =
{ wrap128_setBounds_cap_BITS_113_TO_82_AND_0_CON_ETC___d98 &&
_0b0_CONCAT_wrap128_setBounds_cap_BITS_113_TO_8_ETC___d105,
wrap128_setBounds_cap[114:82],
result_cap_addrBits__h4434,
wrap128_setBounds_cap[73:33],
wrap128_setBounds_length[31] || wrap128_setBounds_length[30] ||
wrap128_setBounds_length[29] ||
wrap128_setBounds_length[28] ||
wrap128_setBounds_length[27] ||
wrap128_setBounds_length[26] ||
wrap128_setBounds_length[25] ||
wrap128_setBounds_length[24] ||
wrap128_setBounds_length[23] ||
wrap128_setBounds_length[22] ||
wrap128_setBounds_length[21] ||
wrap128_setBounds_length[20] ||
wrap128_setBounds_length[19] ||
wrap128_setBounds_length[18] ||
wrap128_setBounds_length[17] ||
wrap128_setBounds_length[16] ||
wrap128_setBounds_length[15] ||
wrap128_setBounds_length[14] ||
wrap128_setBounds_length[13] ||
wrap128_setBounds_length[12] ||
wrap128_setBounds_length[11] ||
wrap128_setBounds_length[10] ||
wrap128_setBounds_length[9] ||
wrap128_setBounds_length[8] ||
wrap128_setBounds_length[7] ||
wrap128_setBounds_length[6],
IF_wrap128_setBounds_length_AND_15_CONCAT_INV__ETC___d190,
IF_NOT_wrap128_setBounds_length_BIT_31_1_2_AND_ETC___d212,
repBound__h4867,
IF_NOT_wrap128_setBounds_length_BIT_31_1_2_AND_ETC___d221,
IF_NOT_wrap128_setBounds_length_BIT_31_1_2_AND_ETC___d222,
IF_wrap128_setBounds_length_AND_15_CONCAT_INV__ETC___d224,
IF_IF_NOT_wrap128_setBounds_length_BIT_31_1_2__ETC___d234 } ;
// remaining internal signals
assign IF_IF_NOT_wrap128_setBounds_length_BIT_31_1_2__ETC___d234 =
{ (IF_NOT_wrap128_setBounds_length_BIT_31_1_2_AND_ETC___d221 ==
IF_wrap128_setBounds_length_AND_15_CONCAT_INV__ETC___d224) ?
2'd0 :
((IF_NOT_wrap128_setBounds_length_BIT_31_1_2_AND_ETC___d221 &&
!IF_wrap128_setBounds_length_AND_15_CONCAT_INV__ETC___d224) ?
2'd1 :
2'd3),
(IF_NOT_wrap128_setBounds_length_BIT_31_1_2_AND_ETC___d222 ==
IF_wrap128_setBounds_length_AND_15_CONCAT_INV__ETC___d224) ?
2'd0 :
((IF_NOT_wrap128_setBounds_length_BIT_31_1_2_AND_ETC___d222 &&
!IF_wrap128_setBounds_length_AND_15_CONCAT_INV__ETC___d224) ?
2'd1 :
2'd3) } ;
assign IF_NOT_wrap128_setBounds_length_BIT_31_1_2_AND_ETC___d212 =
(!wrap128_setBounds_length[31] &&
!wrap128_setBounds_length[30] &&
!wrap128_setBounds_length[29] &&
!wrap128_setBounds_length[28] &&
!wrap128_setBounds_length[27] &&
!wrap128_setBounds_length[26] &&
!wrap128_setBounds_length[25] &&
!wrap128_setBounds_length[24] &&
!wrap128_setBounds_length[23] &&
!wrap128_setBounds_length[22] &&
!wrap128_setBounds_length[21] &&
!wrap128_setBounds_length[20] &&
!wrap128_setBounds_length[19] &&
!wrap128_setBounds_length[18] &&
!wrap128_setBounds_length[17] &&
!wrap128_setBounds_length[16] &&
!wrap128_setBounds_length[15] &&
!wrap128_setBounds_length[14] &&
!wrap128_setBounds_length[13] &&
!wrap128_setBounds_length[12] &&
!wrap128_setBounds_length[11] &&
!wrap128_setBounds_length[10] &&
!wrap128_setBounds_length[9] &&
!wrap128_setBounds_length[8] &&
!wrap128_setBounds_length[7] &&
!wrap128_setBounds_length[6]) ?
{ ret_bounds_topBits__h4829, x__h4615[7:0] } :
{ ret_bounds_topBits__h4600[7:3],
3'd0,
ret_bounds_baseBits__h4780 } ;
assign IF_NOT_wrap128_setBounds_length_BIT_31_1_2_AND_ETC___d221 =
x__h4877[7:5] < repBound__h4867 ;
assign IF_NOT_wrap128_setBounds_length_BIT_31_1_2_AND_ETC___d222 =
x__h4874[7:5] < repBound__h4867 ;
assign IF_wrap128_setBounds_length_AND_15_CONCAT_INV__ETC___d190 =
(wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d130 &&
(wrap128_setBounds_length[31] || wrap128_setBounds_length[30] ||
wrap128_setBounds_length[29] ||
wrap128_setBounds_length[28] ||
wrap128_setBounds_length[27] ||
wrap128_setBounds_length[26] ||
wrap128_setBounds_length[25] ||
wrap128_setBounds_length[24] ||
wrap128_setBounds_length[23] ||
wrap128_setBounds_length[22] ||
wrap128_setBounds_length[21] ||
wrap128_setBounds_length[20] ||
wrap128_setBounds_length[19] ||
wrap128_setBounds_length[18] ||
wrap128_setBounds_length[17] ||
wrap128_setBounds_length[16] ||
wrap128_setBounds_length[15] ||
wrap128_setBounds_length[14] ||
wrap128_setBounds_length[13] ||
wrap128_setBounds_length[12] ||
wrap128_setBounds_length[11] ||
wrap128_setBounds_length[10] ||
wrap128_setBounds_length[9] ||
wrap128_setBounds_length[8] ||
wrap128_setBounds_length[7] ||
wrap128_setBounds_length[6])) ?
_25_MINUS_0_CONCAT_IF_wrap128_setBounds_length__ETC___d183 +
6'd1 :
_25_MINUS_0_CONCAT_IF_wrap128_setBounds_length__ETC___d183 ;
assign IF_wrap128_setBounds_length_AND_15_CONCAT_INV__ETC___d224 =
result_cap_addrBits__h4434[7:5] < repBound__h4867 ;
assign NOT_0_CONCAT_wrap128_setBounds_length_OR_0_CON_ETC___d122 =
(mwLsbMask__h100 & top__h87) != (x__h4494 ^ y__h4495) ;
assign NOT_0b0_CONCAT_wrap128_setBounds_cap_BITS_113__ETC___d191 =
(top__h87 & lmaskLor__h91) != 34'd0 &&
(wrap128_setBounds_length[31] || wrap128_setBounds_length[30] ||
wrap128_setBounds_length[29] ||
wrap128_setBounds_length[28] ||
wrap128_setBounds_length[27] ||
wrap128_setBounds_length[26] ||
wrap128_setBounds_length[25] ||
wrap128_setBounds_length[24] ||
wrap128_setBounds_length[23] ||
wrap128_setBounds_length[22] ||
wrap128_setBounds_length[21] ||
wrap128_setBounds_length[20] ||
wrap128_setBounds_length[19] ||
wrap128_setBounds_length[18] ||
wrap128_setBounds_length[17] ||
wrap128_setBounds_length[16] ||
wrap128_setBounds_length[15] ||
wrap128_setBounds_length[14] ||
wrap128_setBounds_length[13] ||
wrap128_setBounds_length[12] ||
wrap128_setBounds_length[11] ||
wrap128_setBounds_length[10] ||
wrap128_setBounds_length[9] ||
wrap128_setBounds_length[8] ||
wrap128_setBounds_length[7] ||
wrap128_setBounds_length[6]) ;
assign NOT_0b0_CONCAT_wrap128_setBounds_cap_BITS_113__ETC___d202 =
(top__h87 & lmaskLo__h92) != 34'd0 &&
(wrap128_setBounds_length[31] || wrap128_setBounds_length[30] ||
wrap128_setBounds_length[29] ||
wrap128_setBounds_length[28] ||
wrap128_setBounds_length[27] ||
wrap128_setBounds_length[26] ||
wrap128_setBounds_length[25] ||
wrap128_setBounds_length[24] ||
wrap128_setBounds_length[23] ||
wrap128_setBounds_length[22] ||
wrap128_setBounds_length[21] ||
wrap128_setBounds_length[20] ||
wrap128_setBounds_length[19] ||
wrap128_setBounds_length[18] ||
wrap128_setBounds_length[17] ||
wrap128_setBounds_length[16] ||
wrap128_setBounds_length[15] ||
wrap128_setBounds_length[14] ||
wrap128_setBounds_length[13] ||
wrap128_setBounds_length[12] ||
wrap128_setBounds_length[11] ||
wrap128_setBounds_length[10] ||
wrap128_setBounds_length[9] ||
wrap128_setBounds_length[8] ||
wrap128_setBounds_length[7] ||
wrap128_setBounds_length[6]) ;
assign _0b0_CONCAT_wrap128_setBounds_cap_BITS_113_TO_8_ETC___d105 =
(top__h87 & lmaskLor__h91) == 34'd0 ||
!wrap128_setBounds_length[31] && !wrap128_setBounds_length[30] &&
!wrap128_setBounds_length[29] &&
!wrap128_setBounds_length[28] &&
!wrap128_setBounds_length[27] &&
!wrap128_setBounds_length[26] &&
!wrap128_setBounds_length[25] &&
!wrap128_setBounds_length[24] &&
!wrap128_setBounds_length[23] &&
!wrap128_setBounds_length[22] &&
!wrap128_setBounds_length[21] &&
!wrap128_setBounds_length[20] &&
!wrap128_setBounds_length[19] &&
!wrap128_setBounds_length[18] &&
!wrap128_setBounds_length[17] &&
!wrap128_setBounds_length[16] &&
!wrap128_setBounds_length[15] &&
!wrap128_setBounds_length[14] &&
!wrap128_setBounds_length[13] &&
!wrap128_setBounds_length[12] &&
!wrap128_setBounds_length[11] &&
!wrap128_setBounds_length[10] &&
!wrap128_setBounds_length[9] &&
!wrap128_setBounds_length[8] &&
!wrap128_setBounds_length[7] &&
!wrap128_setBounds_length[6] ;
assign _25_MINUS_0_CONCAT_IF_wrap128_setBounds_length__ETC___d183 =
6'd25 -
{ 1'd0,
wrap128_setBounds_length[31] ?
5'd0 :
(wrap128_setBounds_length[30] ?
5'd1 :
(wrap128_setBounds_length[29] ?
5'd2 :
(wrap128_setBounds_length[28] ?
5'd3 :
(wrap128_setBounds_length[27] ?
5'd4 :
(wrap128_setBounds_length[26] ?
5'd5 :
(wrap128_setBounds_length[25] ?
5'd6 :
(wrap128_setBounds_length[24] ?
5'd7 :
(wrap128_setBounds_length[23] ?
5'd8 :
(wrap128_setBounds_length[22] ?
5'd9 :
(wrap128_setBounds_length[21] ?
5'd10 :
(wrap128_setBounds_length[20] ?
5'd11 :
(wrap128_setBounds_length[19] ?
5'd12 :
(wrap128_setBounds_length[18] ?
5'd13 :
(wrap128_setBounds_length[17] ?
5'd14 :
(wrap128_setBounds_length[16] ?
5'd15 :
(wrap128_setBounds_length[15] ?
5'd16 :
(wrap128_setBounds_length[14] ?
5'd17 :
(wrap128_setBounds_length[13] ?
5'd18 :
(wrap128_setBounds_length[12] ?
5'd19 :
(wrap128_setBounds_length[11] ?
5'd20 :
(wrap128_setBounds_length[10] ?
5'd21 :
(wrap128_setBounds_length[9] ?
5'd22 :
(wrap128_setBounds_length[8] ?
5'd23 :
(wrap128_setBounds_length[7] ?
5'd24 :
5'd25)))))))))))))))))))))))) } ;
assign _theResult_____3_fst_bounds_topBits__h4604 =
NOT_0b0_CONCAT_wrap128_setBounds_cap_BITS_113__ETC___d202 ?
x__h4798[8:1] + 8'b00001000 :
x__h4798[8:1] ;
assign base__h84 = { 2'b0, wrap128_setBounds_cap[113:82] } ;
assign len__h86 = { 2'b0, wrap128_setBounds_length } ;
assign lmaskLo__h92 =
{ 5'd0,
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d16[31:3] } ;
assign lmaskLor__h91 =
{ 6'd0,
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d16[31:4] } ;
assign mwLsbMask__h100 = lmaskLor__h91 ^ lmaskLo__h92 ;
assign repBound__h4867 = x__h4874[7:5] - 3'b001 ;
assign result_cap_addrBits__h4434 =
(wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d130 &&
(wrap128_setBounds_length[31] || wrap128_setBounds_length[30] ||
wrap128_setBounds_length[29] ||
wrap128_setBounds_length[28] ||
wrap128_setBounds_length[27] ||
wrap128_setBounds_length[26] ||
wrap128_setBounds_length[25] ||
wrap128_setBounds_length[24] ||
wrap128_setBounds_length[23] ||
wrap128_setBounds_length[22] ||
wrap128_setBounds_length[21] ||
wrap128_setBounds_length[20] ||
wrap128_setBounds_length[19] ||
wrap128_setBounds_length[18] ||
wrap128_setBounds_length[17] ||
wrap128_setBounds_length[16] ||
wrap128_setBounds_length[15] ||
wrap128_setBounds_length[14] ||
wrap128_setBounds_length[13] ||
wrap128_setBounds_length[12] ||
wrap128_setBounds_length[11] ||
wrap128_setBounds_length[10] ||
wrap128_setBounds_length[9] ||
wrap128_setBounds_length[8] ||
wrap128_setBounds_length[7] ||
wrap128_setBounds_length[6])) ?
x__h4615[8:1] :
x__h4615[7:0] ;
assign ret_bounds_baseBits__h4780 =
{ result_cap_addrBits__h4434[7:3], 3'd0 } ;
assign ret_bounds_topBits__h4600 =
(wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d130 &&
(wrap128_setBounds_length[31] || wrap128_setBounds_length[30] ||
wrap128_setBounds_length[29] ||
wrap128_setBounds_length[28] ||
wrap128_setBounds_length[27] ||
wrap128_setBounds_length[26] ||
wrap128_setBounds_length[25] ||
wrap128_setBounds_length[24] ||
wrap128_setBounds_length[23] ||
wrap128_setBounds_length[22] ||
wrap128_setBounds_length[21] ||
wrap128_setBounds_length[20] ||
wrap128_setBounds_length[19] ||
wrap128_setBounds_length[18] ||
wrap128_setBounds_length[17] ||
wrap128_setBounds_length[16] ||
wrap128_setBounds_length[15] ||
wrap128_setBounds_length[14] ||
wrap128_setBounds_length[13] ||
wrap128_setBounds_length[12] ||
wrap128_setBounds_length[11] ||
wrap128_setBounds_length[10] ||
wrap128_setBounds_length[9] ||
wrap128_setBounds_length[8] ||
wrap128_setBounds_length[7] ||
wrap128_setBounds_length[6])) ?
_theResult_____3_fst_bounds_topBits__h4604 :
ret_bounds_topBits__h4829 ;
assign ret_bounds_topBits__h4829 =
NOT_0b0_CONCAT_wrap128_setBounds_cap_BITS_113__ETC___d191 ?
x__h4837[7:0] :
x__h4798[7:0] ;
assign top__h87 = base__h84 + len__h86 ;
assign wrap128_setBounds_cap_BITS_113_TO_82_AND_0_CON_ETC___d98 =
(wrap128_setBounds_cap[113:82] &
{ 4'd0,
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d16[31:4] }) ==
32'd0 ||
!wrap128_setBounds_length[31] && !wrap128_setBounds_length[30] &&
!wrap128_setBounds_length[29] &&
!wrap128_setBounds_length[28] &&
!wrap128_setBounds_length[27] &&
!wrap128_setBounds_length[26] &&
!wrap128_setBounds_length[25] &&
!wrap128_setBounds_length[24] &&
!wrap128_setBounds_length[23] &&
!wrap128_setBounds_length[22] &&
!wrap128_setBounds_length[21] &&
!wrap128_setBounds_length[20] &&
!wrap128_setBounds_length[19] &&
!wrap128_setBounds_length[18] &&
!wrap128_setBounds_length[17] &&
!wrap128_setBounds_length[16] &&
!wrap128_setBounds_length[15] &&
!wrap128_setBounds_length[14] &&
!wrap128_setBounds_length[13] &&
!wrap128_setBounds_length[12] &&
!wrap128_setBounds_length[11] &&
!wrap128_setBounds_length[10] &&
!wrap128_setBounds_length[9] &&
!wrap128_setBounds_length[8] &&
!wrap128_setBounds_length[7] &&
!wrap128_setBounds_length[6] ;
assign wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d110 =
wrap128_setBounds_length &
{ 4'd15,
~wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d16[31:4] } ;
assign wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d123 =
wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d110 ==
(wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d16 ^
{ 3'd0,
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d16[31:3] }) &&
NOT_0_CONCAT_wrap128_setBounds_length_OR_0_CON_ETC___d122 ;
assign wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d129 =
wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d110 ==
(wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d16 ^
{ 4'd0,
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d16[31:4] }) &&
(NOT_0_CONCAT_wrap128_setBounds_length_OR_0_CON_ETC___d122 ||
(top__h87 & lmaskLor__h91) != 34'd0) ;
assign wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d130 =
wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d123 &&
(top__h87 & lmaskLor__h91) != 34'd0 ||
wrap128_setBounds_length_AND_15_CONCAT_INV_wra_ETC___d129 ;
assign wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d10 =
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d7 |
{ 4'd0,
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d7[31:4] } ;
assign wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d13 =
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d10 |
{ 8'd0,
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d10[31:8] } ;
assign wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d16 =
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d13 |
{ 16'd0,
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d13[31:16] } ;
assign wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d4 =
wrap128_setBounds_length |
{ 1'd0, wrap128_setBounds_length[31:1] } ;
assign wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d7 =
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d4 |
{ 2'd0,
wrap128_setBounds_length_OR_0_CONCAT_wrap128_s_ETC___d4[31:2] } ;
assign x__h4494 = mwLsbMask__h100 & base__h84 ;
assign x__h4615 =
base__h84 >>
_25_MINUS_0_CONCAT_IF_wrap128_setBounds_length__ETC___d183 ;
assign x__h4798 =
top__h87 >>
_25_MINUS_0_CONCAT_IF_wrap128_setBounds_length__ETC___d183 ;
assign x__h4837 = x__h4798[8:0] + 9'b000001000 ;
assign x__h4874 =
(!wrap128_setBounds_length[31] &&
!wrap128_setBounds_length[30] &&
!wrap128_setBounds_length[29] &&
!wrap128_setBounds_length[28] &&
!wrap128_setBounds_length[27] &&
!wrap128_setBounds_length[26] &&
!wrap128_setBounds_length[25] &&
!wrap128_setBounds_length[24] &&
!wrap128_setBounds_length[23] &&
!wrap128_setBounds_length[22] &&
!wrap128_setBounds_length[21] &&
!wrap128_setBounds_length[20] &&
!wrap128_setBounds_length[19] &&
!wrap128_setBounds_length[18] &&
!wrap128_setBounds_length[17] &&
!wrap128_setBounds_length[16] &&
!wrap128_setBounds_length[15] &&
!wrap128_setBounds_length[14] &&
!wrap128_setBounds_length[13] &&
!wrap128_setBounds_length[12] &&
!wrap128_setBounds_length[11] &&
!wrap128_setBounds_length[10] &&
!wrap128_setBounds_length[9] &&
!wrap128_setBounds_length[8] &&
!wrap128_setBounds_length[7] &&
!wrap128_setBounds_length[6]) ?
result_cap_addrBits__h4434 :
ret_bounds_baseBits__h4780 ;
assign x__h4877 =
(!wrap128_setBounds_length[31] &&
!wrap128_setBounds_length[30] &&
!wrap128_setBounds_length[29] &&
!wrap128_setBounds_length[28] &&
!wrap128_setBounds_length[27] &&
!wrap128_setBounds_length[26] &&
!wrap128_setBounds_length[25] &&
!wrap128_setBounds_length[24] &&
!wrap128_setBounds_length[23] &&
!wrap128_setBounds_length[22] &&
!wrap128_setBounds_length[21] &&
!wrap128_setBounds_length[20] &&
!wrap128_setBounds_length[19] &&
!wrap128_setBounds_length[18] &&
!wrap128_setBounds_length[17] &&
!wrap128_setBounds_length[16] &&
!wrap128_setBounds_length[15] &&
!wrap128_setBounds_length[14] &&
!wrap128_setBounds_length[13] &&
!wrap128_setBounds_length[12] &&
!wrap128_setBounds_length[11] &&
!wrap128_setBounds_length[10] &&
!wrap128_setBounds_length[9] &&
!wrap128_setBounds_length[8] &&
!wrap128_setBounds_length[7] &&
!wrap128_setBounds_length[6]) ?
ret_bounds_topBits__h4600 :
{ ret_bounds_topBits__h4600[7:3], 3'd0 } ;
assign y__h4495 = mwLsbMask__h100 & len__h86 ;
endmodule // module_wrap128_setBounds

48
module_wrap128_setFlags.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_setFlags O 115
// wrap128_setFlags_cap I 115
// wrap128_setFlags_flags I 1
//
// Combinational paths from inputs to outputs:
// (wrap128_setFlags_cap, wrap128_setFlags_flags) -> wrap128_setFlags
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_setFlags(wrap128_setFlags_cap,
wrap128_setFlags_flags,
wrap128_setFlags);
// value method wrap128_setFlags
input [114 : 0] wrap128_setFlags_cap;
input wrap128_setFlags_flags;
output [114 : 0] wrap128_setFlags;
// signals for module outputs
wire [114 : 0] wrap128_setFlags;
// value method wrap128_setFlags
assign wrap128_setFlags =
{ wrap128_setFlags_cap[114:62],
wrap128_setFlags_flags,
wrap128_setFlags_cap[60:0] } ;
endmodule // module_wrap128_setFlags

49
module_wrap128_setHardPerms.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_setHardPerms O 115
// wrap128_setHardPerms_cap I 115
// wrap128_setHardPerms_hardperms I 12
//
// Combinational paths from inputs to outputs:
// (wrap128_setHardPerms_cap,
// wrap128_setHardPerms_hardperms) -> wrap128_setHardPerms
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_setHardPerms(wrap128_setHardPerms_cap,
wrap128_setHardPerms_hardperms,
wrap128_setHardPerms);
// value method wrap128_setHardPerms
input [114 : 0] wrap128_setHardPerms_cap;
input [11 : 0] wrap128_setHardPerms_hardperms;
output [114 : 0] wrap128_setHardPerms;
// signals for module outputs
wire [114 : 0] wrap128_setHardPerms;
// value method wrap128_setHardPerms
assign wrap128_setHardPerms =
{ wrap128_setHardPerms_cap[114:74],
wrap128_setHardPerms_hardperms,
wrap128_setHardPerms_cap[61:0] } ;
endmodule // module_wrap128_setHardPerms

64
module_wrap128_setKind.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_setKind O 115
// wrap128_setKind_cap I 115
// wrap128_setKind_kind I 7
//
// Combinational paths from inputs to outputs:
// (wrap128_setKind_cap, wrap128_setKind_kind) -> wrap128_setKind
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_setKind(wrap128_setKind_cap,
wrap128_setKind_kind,
wrap128_setKind);
// value method wrap128_setKind
input [114 : 0] wrap128_setKind_cap;
input [6 : 0] wrap128_setKind_kind;
output [114 : 0] wrap128_setKind;
// signals for module outputs
wire [114 : 0] wrap128_setKind;
// remaining internal signals
reg [3 : 0] CASE_wrap128_setKind_kind_BITS_6_TO_4_0_15_1_1_ETC__q1;
// value method wrap128_setKind
assign wrap128_setKind =
{ wrap128_setKind_cap[114:61],
CASE_wrap128_setKind_kind_BITS_6_TO_4_0_15_1_1_ETC__q1,
wrap128_setKind_cap[56:0] } ;
// remaining internal signals
always@(wrap128_setKind_kind)
begin
case (wrap128_setKind_kind[6:4])
3'd0: CASE_wrap128_setKind_kind_BITS_6_TO_4_0_15_1_1_ETC__q1 = 4'd15;
3'd1: CASE_wrap128_setKind_kind_BITS_6_TO_4_0_15_1_1_ETC__q1 = 4'd14;
3'd2: CASE_wrap128_setKind_kind_BITS_6_TO_4_0_15_1_1_ETC__q1 = 4'd13;
3'd3: CASE_wrap128_setKind_kind_BITS_6_TO_4_0_15_1_1_ETC__q1 = 4'd12;
default: CASE_wrap128_setKind_kind_BITS_6_TO_4_0_15_1_1_ETC__q1 =
wrap128_setKind_kind[3:0];
endcase
end
endmodule // module_wrap128_setKind

129
module_wrap128_setOffset.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_setOffset O 116
// wrap128_setOffset_cap I 115
// wrap128_setOffset_offset I 32
//
// Combinational paths from inputs to outputs:
// (wrap128_setOffset_cap, wrap128_setOffset_offset) -> wrap128_setOffset
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_setOffset(wrap128_setOffset_cap,
wrap128_setOffset_offset,
wrap128_setOffset);
// value method wrap128_setOffset
input [114 : 0] wrap128_setOffset_cap;
input [31 : 0] wrap128_setOffset_offset;
output [115 : 0] wrap128_setOffset;
// signals for module outputs
wire [115 : 0] wrap128_setOffset;
// remaining internal signals
reg [1 : 0] mask__h560;
wire [31 : 0] addBase__h594, result_d_address__h572, x__h488;
wire [23 : 0] highOffsetBits__h80, mask__h595, signBits__h77, x__h107;
wire [9 : 0] x__h645;
wire [7 : 0] newAddrBits__h559,
result_d_addrBits__h573,
toBoundsM1__h90,
toBounds__h89;
wire [3 : 0] IF_wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_w_ETC___d62;
wire [2 : 0] repBound__h826;
wire IF_wrap128_setOffset_cap_BITS_31_TO_26_EQ_26_6_ETC___d52,
IF_wrap128_setOffset_offset_BIT_31_THEN_NOT_wr_ETC___d19,
wrap128_setOffset_cap_BITS_17_TO_15_6_ULT_wrap_ETC___d50,
wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_wrap_ETC___d49;
// value method wrap128_setOffset
assign wrap128_setOffset =
{ highOffsetBits__h80 == 24'd0 &&
IF_wrap128_setOffset_offset_BIT_31_THEN_NOT_wr_ETC___d19 ||
wrap128_setOffset_cap[31:26] >= 6'd24,
(highOffsetBits__h80 == 24'd0 &&
IF_wrap128_setOffset_offset_BIT_31_THEN_NOT_wr_ETC___d19 ||
wrap128_setOffset_cap[31:26] >= 6'd24) &&
wrap128_setOffset_cap[114],
result_d_address__h572,
result_d_addrBits__h573,
wrap128_setOffset_cap[73:10],
repBound__h826,
wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_wrap_ETC___d49,
wrap128_setOffset_cap_BITS_17_TO_15_6_ULT_wrap_ETC___d50,
IF_wrap128_setOffset_cap_BITS_31_TO_26_EQ_26_6_ETC___d52,
IF_wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_w_ETC___d62 } ;
// remaining internal signals
assign IF_wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_w_ETC___d62 =
{ (wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_wrap_ETC___d49 ==
IF_wrap128_setOffset_cap_BITS_31_TO_26_EQ_26_6_ETC___d52) ?
2'd0 :
((wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_wrap_ETC___d49 &&
!IF_wrap128_setOffset_cap_BITS_31_TO_26_EQ_26_6_ETC___d52) ?
2'd1 :
2'd3),
(wrap128_setOffset_cap_BITS_17_TO_15_6_ULT_wrap_ETC___d50 ==
IF_wrap128_setOffset_cap_BITS_31_TO_26_EQ_26_6_ETC___d52) ?
2'd0 :
((wrap128_setOffset_cap_BITS_17_TO_15_6_ULT_wrap_ETC___d50 &&
!IF_wrap128_setOffset_cap_BITS_31_TO_26_EQ_26_6_ETC___d52) ?
2'd1 :
2'd3) } ;
assign IF_wrap128_setOffset_cap_BITS_31_TO_26_EQ_26_6_ETC___d52 =
result_d_addrBits__h573[7:5] < repBound__h826 ;
assign IF_wrap128_setOffset_offset_BIT_31_THEN_NOT_wr_ETC___d19 =
wrap128_setOffset_offset[31] ?
x__h488[7:0] >= toBounds__h89 :
x__h488[7:0] <= toBoundsM1__h90 ;
assign addBase__h594 =
{ {22{x__h645[9]}}, x__h645 } << wrap128_setOffset_cap[31:26] ;
assign highOffsetBits__h80 = x__h107 & mask__h595 ;
assign mask__h595 = 24'd16777215 << wrap128_setOffset_cap[31:26] ;
assign newAddrBits__h559 = wrap128_setOffset_cap[17:10] + x__h488[7:0] ;
assign repBound__h826 = wrap128_setOffset_cap[17:15] - 3'b001 ;
assign result_d_addrBits__h573 = { mask__h560, 6'd63 } & newAddrBits__h559 ;
assign result_d_address__h572 =
{ wrap128_setOffset_cap[113:90] & mask__h595, 8'd0 } +
addBase__h594 +
wrap128_setOffset_offset ;
assign signBits__h77 = {24{wrap128_setOffset_offset[31]}} ;
assign toBoundsM1__h90 = { 3'b110, ~wrap128_setOffset_cap[14:10] } ;
assign toBounds__h89 = 8'd224 - { 3'b0, wrap128_setOffset_cap[14:10] } ;
assign wrap128_setOffset_cap_BITS_17_TO_15_6_ULT_wrap_ETC___d50 =
wrap128_setOffset_cap[17:15] < repBound__h826 ;
assign wrap128_setOffset_cap_BITS_25_TO_23_8_ULT_wrap_ETC___d49 =
wrap128_setOffset_cap[25:23] < repBound__h826 ;
assign x__h107 = wrap128_setOffset_offset[31:8] ^ signBits__h77 ;
assign x__h488 = wrap128_setOffset_offset >> wrap128_setOffset_cap[31:26] ;
assign x__h645 =
{ wrap128_setOffset_cap[1:0], wrap128_setOffset_cap[17:10] } ;
always@(wrap128_setOffset_cap)
begin
case (wrap128_setOffset_cap[31:26])
6'd25: mask__h560 = 2'b01;
6'd26: mask__h560 = 2'b0;
default: mask__h560 = 2'b11;
endcase
end
endmodule // module_wrap128_setOffset

48
module_wrap128_setPerms.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_setPerms O 115
// wrap128_setPerms_cap I 115
// wrap128_setPerms_perms I 31
//
// Combinational paths from inputs to outputs:
// (wrap128_setPerms_cap, wrap128_setPerms_perms) -> wrap128_setPerms
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_setPerms(wrap128_setPerms_cap,
wrap128_setPerms_perms,
wrap128_setPerms);
// value method wrap128_setPerms
input [114 : 0] wrap128_setPerms_cap;
input [30 : 0] wrap128_setPerms_perms;
output [114 : 0] wrap128_setPerms;
// signals for module outputs
wire [114 : 0] wrap128_setPerms;
// value method wrap128_setPerms
assign wrap128_setPerms =
{ wrap128_setPerms_cap[114:74],
wrap128_setPerms_perms[11:0],
wrap128_setPerms_cap[61:0] } ;
endmodule // module_wrap128_setPerms

45
module_wrap128_setSoftPerms.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_setSoftPerms O 115
// wrap128_setSoftPerms_cap I 115
// wrap128_setSoftPerms_softperms I 16 unused
//
// Combinational paths from inputs to outputs:
// wrap128_setSoftPerms_cap -> wrap128_setSoftPerms
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_setSoftPerms(wrap128_setSoftPerms_cap,
wrap128_setSoftPerms_softperms,
wrap128_setSoftPerms);
// value method wrap128_setSoftPerms
input [114 : 0] wrap128_setSoftPerms_cap;
input [15 : 0] wrap128_setSoftPerms_softperms;
output [114 : 0] wrap128_setSoftPerms;
// signals for module outputs
wire [114 : 0] wrap128_setSoftPerms;
// value method wrap128_setSoftPerms
assign wrap128_setSoftPerms = wrap128_setSoftPerms_cap ;
endmodule // module_wrap128_setSoftPerms

46
module_wrap128_setValidCap.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_setValidCap O 115
// wrap128_setValidCap_cap I 115
// wrap128_setValidCap_valid I 1
//
// Combinational paths from inputs to outputs:
// (wrap128_setValidCap_cap, wrap128_setValidCap_valid) -> wrap128_setValidCap
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_setValidCap(wrap128_setValidCap_cap,
wrap128_setValidCap_valid,
wrap128_setValidCap);
// value method wrap128_setValidCap
input [114 : 0] wrap128_setValidCap_cap;
input wrap128_setValidCap_valid;
output [114 : 0] wrap128_setValidCap;
// signals for module outputs
wire [114 : 0] wrap128_setValidCap;
// value method wrap128_setValidCap
assign wrap128_setValidCap =
{ wrap128_setValidCap_valid, wrap128_setValidCap_cap[113:0] } ;
endmodule // module_wrap128_setValidCap

66
module_wrap128_toMem.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_toMem O 89
// wrap128_toMem_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap128_toMem_cap -> wrap128_toMem
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_toMem(wrap128_toMem_cap,
wrap128_toMem);
// value method wrap128_toMem
input [114 : 0] wrap128_toMem_cap;
output [88 : 0] wrap128_toMem;
// signals for module outputs
wire [88 : 0] wrap128_toMem;
// remaining internal signals
wire [87 : 0] x__h467;
wire [13 : 0] IF_wrap128_toMem_cap_BIT_32_THEN_wrap128_toMem_ETC___d15;
// value method wrap128_toMem
assign wrap128_toMem = { wrap128_toMem_cap[114], x__h467 } ;
// remaining internal signals
assign IF_wrap128_toMem_cap_BIT_32_THEN_wrap128_toMem_ETC___d15 =
wrap128_toMem_cap[32] ?
{ wrap128_toMem_cap[23:21],
wrap128_toMem_cap[31:29],
wrap128_toMem_cap[17:13],
wrap128_toMem_cap[28:26] } :
wrap128_toMem_cap[23:10] ;
assign x__h467 =
{ wrap128_toMem_cap[73:61],
~wrap128_toMem_cap[60:57],
24'hAAAAAA ^ 24'hAAAAAA,
~wrap128_toMem_cap[32],
IF_wrap128_toMem_cap_BIT_32_THEN_wrap128_toMem_ETC___d15[13:10],
~IF_wrap128_toMem_cap_BIT_32_THEN_wrap128_toMem_ETC___d15[9:8],
IF_wrap128_toMem_cap_BIT_32_THEN_wrap128_toMem_ETC___d15[7:2],
~IF_wrap128_toMem_cap_BIT_32_THEN_wrap128_toMem_ETC___d15[1],
IF_wrap128_toMem_cap_BIT_32_THEN_wrap128_toMem_ETC___d15[0],
wrap128_toMem_cap[113:82] } ;
endmodule // module_wrap128_toMem

45
module_wrap128_validAsType.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:11:39 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap128_validAsType O 1
// wrap128_validAsType_dummy I 115 unused
// wrap128_validAsType_checkType I 32
//
// Combinational paths from inputs to outputs:
// wrap128_validAsType_checkType -> wrap128_validAsType
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap128_validAsType(wrap128_validAsType_dummy,
wrap128_validAsType_checkType,
wrap128_validAsType);
// value method wrap128_validAsType
input [114 : 0] wrap128_validAsType_dummy;
input [31 : 0] wrap128_validAsType_checkType;
output wrap128_validAsType;
// signals for module outputs
wire wrap128_validAsType;
// value method wrap128_validAsType
assign wrap128_validAsType = wrap128_validAsType_checkType <= 32'd11 ;
endmodule // module_wrap128_validAsType

38
module_wrap64_almightyCap.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:26 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_almightyCap O 115 const
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_almightyCap(wrap64_almightyCap);
// value method wrap64_almightyCap
output [114 : 0] wrap64_almightyCap;
// signals for module outputs
wire [114 : 0] wrap64_almightyCap;
// value method wrap64_almightyCap
assign wrap64_almightyCap = 115'h40000000003FFDF555555690003F0 ;
endmodule // module_wrap64_almightyCap

115
module_wrap64_fromMem.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:26 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_fromMem O 115
// wrap64_fromMem_mem_cap I 89
//
// Combinational paths from inputs to outputs:
// wrap64_fromMem_mem_cap -> wrap64_fromMem
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_fromMem(wrap64_fromMem_mem_cap,
wrap64_fromMem);
// value method wrap64_fromMem
input [88 : 0] wrap64_fromMem_mem_cap;
output [114 : 0] wrap64_fromMem;
// signals for module outputs
wire [114 : 0] wrap64_fromMem;
// remaining internal signals
wire [88 : 0] thin__h113;
wire [31 : 0] x__h428;
wire [21 : 0] IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d33;
wire [7 : 0] bounds_topBits__h585,
res_addrBits__h131,
x__h618,
x__h638,
x__h653;
wire [5 : 0] x__h462;
wire [4 : 0] IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d52;
wire [2 : 0] repBound__h698, tb__h695;
wire [1 : 0] carry_out__h553,
impliedTopBits__h555,
len_correction__h554,
x__h635;
wire IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d39,
IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d40,
IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d42;
// value method wrap64_fromMem
assign wrap64_fromMem =
{ thin__h113[88],
thin__h113[31:0],
res_addrBits__h131,
thin__h113[87:46],
IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d33,
repBound__h698,
IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d39,
IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d40,
IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d52 } ;
// remaining internal signals
assign IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d33 =
{ thin__h113[46] ? x__h462 : 6'd0, x__h618, x__h638 } ;
assign IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d39 =
tb__h695 < repBound__h698 ;
assign IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d40 =
x__h638[7:5] < repBound__h698 ;
assign IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d42 =
res_addrBits__h131[7:5] < repBound__h698 ;
assign IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d52 =
{ IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d42,
(IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d39 ==
IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d42) ?
2'd0 :
((IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d39 &&
!IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d42) ?
2'd1 :
2'd3),
(IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d40 ==
IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d42) ?
2'd0 :
((IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d40 &&
!IF_wrap64_fromMem_mem_cap_XOR_15_CONCAT_DONTCA_ETC___d42) ?
2'd1 :
2'd3) } ;
assign bounds_topBits__h585 = { 2'h2, thin__h113[45:43], 3'd0 } ;
assign carry_out__h553 = (x__h653[5:0] < x__h638[5:0]) ? 2'b01 : 2'b0 ;
assign impliedTopBits__h555 = x__h635 + len_correction__h554 ;
assign len_correction__h554 = thin__h113[46] ? 2'b01 : 2'b0 ;
assign repBound__h698 = x__h638[7:5] - 3'b001 ;
assign res_addrBits__h131 =
thin__h113[46] ? x__h428[7:0] : thin__h113[7:0] ;
assign tb__h695 = { impliedTopBits__h555, x__h653[5] } ;
assign thin__h113 = wrap64_fromMem_mem_cap ^ 89'h00007D55555430200000000 ;
assign x__h428 = thin__h113[31:0] >> x__h462 ;
assign x__h462 = { thin__h113[42:40], thin__h113[34:32] } ;
assign x__h618 = { impliedTopBits__h555, x__h653[5:0] } ;
assign x__h635 = x__h638[7:6] + carry_out__h553 ;
assign x__h638 =
thin__h113[46] ?
{ thin__h113[39:35], 3'd0 } :
thin__h113[39:32] ;
assign x__h653 = thin__h113[46] ? bounds_topBits__h585 : thin__h113[47:40] ;
endmodule // module_wrap64_fromMem

42
module_wrap64_getAddr.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_getAddr O 32
// wrap64_getAddr_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap64_getAddr_cap -> wrap64_getAddr
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_getAddr(wrap64_getAddr_cap,
wrap64_getAddr);
// value method wrap64_getAddr
input [114 : 0] wrap64_getAddr_cap;
output [31 : 0] wrap64_getAddr;
// signals for module outputs
wire [31 : 0] wrap64_getAddr;
// value method wrap64_getAddr
assign wrap64_getAddr = wrap64_getAddr_cap[113:82] ;
endmodule // module_wrap64_getAddr

54
module_wrap64_getBase.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_getBase O 32
// wrap64_getBase_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap64_getBase_cap -> wrap64_getBase
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_getBase(wrap64_getBase_cap,
wrap64_getBase);
// value method wrap64_getBase
input [114 : 0] wrap64_getBase_cap;
output [31 : 0] wrap64_getBase;
// signals for module outputs
wire [31 : 0] wrap64_getBase;
// remaining internal signals
wire [31 : 0] addBase__h64;
wire [23 : 0] mask__h65;
wire [9 : 0] x__h167;
// value method wrap64_getBase
assign wrap64_getBase =
{ wrap64_getBase_cap[113:90] & mask__h65, 8'd0 } + addBase__h64 ;
// remaining internal signals
assign addBase__h64 =
{ {22{x__h167[9]}}, x__h167 } << wrap64_getBase_cap[31:26] ;
assign mask__h65 = 24'd16777215 << wrap64_getBase_cap[31:26] ;
assign x__h167 = { wrap64_getBase_cap[1:0], wrap64_getBase_cap[17:10] } ;
endmodule // module_wrap64_getBase

42
module_wrap64_getFlags.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_getFlags O 1
// wrap64_getFlags_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap64_getFlags_cap -> wrap64_getFlags
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_getFlags(wrap64_getFlags_cap,
wrap64_getFlags);
// value method wrap64_getFlags
input [114 : 0] wrap64_getFlags_cap;
output wrap64_getFlags;
// signals for module outputs
wire wrap64_getFlags;
// value method wrap64_getFlags
assign wrap64_getFlags = wrap64_getFlags_cap[61] ;
endmodule // module_wrap64_getFlags

42
module_wrap64_getHardPerms.v Normal file
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@@ -0,0 +1,42 @@
//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_getHardPerms O 12
// wrap64_getHardPerms_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap64_getHardPerms_cap -> wrap64_getHardPerms
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_getHardPerms(wrap64_getHardPerms_cap,
wrap64_getHardPerms);
// value method wrap64_getHardPerms
input [114 : 0] wrap64_getHardPerms_cap;
output [11 : 0] wrap64_getHardPerms;
// signals for module outputs
wire [11 : 0] wrap64_getHardPerms;
// value method wrap64_getHardPerms
assign wrap64_getHardPerms = wrap64_getHardPerms_cap[73:62] ;
endmodule // module_wrap64_getHardPerms

59
module_wrap64_getKind.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_getKind O 7
// wrap64_getKind_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap64_getKind_cap -> wrap64_getKind
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_getKind(wrap64_getKind_cap,
wrap64_getKind);
// value method wrap64_getKind
input [114 : 0] wrap64_getKind_cap;
output [6 : 0] wrap64_getKind;
// signals for module outputs
wire [6 : 0] wrap64_getKind;
// remaining internal signals
reg [2 : 0] CASE_wrap64_getKind_cap_BITS_60_TO_57_12_3_13__ETC__q1;
// value method wrap64_getKind
assign wrap64_getKind =
{ CASE_wrap64_getKind_cap_BITS_60_TO_57_12_3_13__ETC__q1,
wrap64_getKind_cap[60:57] } ;
// remaining internal signals
always@(wrap64_getKind_cap)
begin
case (wrap64_getKind_cap[60:57])
4'd12: CASE_wrap64_getKind_cap_BITS_60_TO_57_12_3_13__ETC__q1 = 3'd3;
4'd13: CASE_wrap64_getKind_cap_BITS_60_TO_57_12_3_13__ETC__q1 = 3'd2;
4'd14: CASE_wrap64_getKind_cap_BITS_60_TO_57_12_3_13__ETC__q1 = 3'd1;
4'd15: CASE_wrap64_getKind_cap_BITS_60_TO_57_12_3_13__ETC__q1 = 3'd0;
default: CASE_wrap64_getKind_cap_BITS_60_TO_57_12_3_13__ETC__q1 = 3'd4;
endcase
end
endmodule // module_wrap64_getKind

57
module_wrap64_getLength.v Normal file
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@@ -0,0 +1,57 @@
//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_getLength O 33
// wrap64_getLength_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap64_getLength_cap -> wrap64_getLength
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_getLength(wrap64_getLength_cap,
wrap64_getLength);
// value method wrap64_getLength
input [114 : 0] wrap64_getLength_cap;
output [32 : 0] wrap64_getLength;
// signals for module outputs
wire [32 : 0] wrap64_getLength;
// remaining internal signals
wire [32 : 0] length__h66;
wire [9 : 0] base__h65, top__h64, x__h125;
// value method wrap64_getLength
assign wrap64_getLength =
(wrap64_getLength_cap[31:26] < 6'd26) ?
length__h66 :
33'h1FFFFFFFF ;
// remaining internal signals
assign base__h65 =
{ wrap64_getLength_cap[1:0], wrap64_getLength_cap[17:10] } ;
assign length__h66 = { 23'd0, x__h125 } << wrap64_getLength_cap[31:26] ;
assign top__h64 =
{ wrap64_getLength_cap[3:2], wrap64_getLength_cap[25:18] } ;
assign x__h125 = top__h64 - base__h65 ;
endmodule // module_wrap64_getLength

56
module_wrap64_getOffset.v Normal file
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@@ -0,0 +1,56 @@
//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_getOffset O 32
// wrap64_getOffset_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap64_getOffset_cap -> wrap64_getOffset
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_getOffset(wrap64_getOffset_cap,
wrap64_getOffset);
// value method wrap64_getOffset
input [114 : 0] wrap64_getOffset_cap;
output [31 : 0] wrap64_getOffset;
// signals for module outputs
wire [31 : 0] wrap64_getOffset;
// remaining internal signals
wire [31 : 0] addrLSB__h68, x__h204, x__h79, x__h81, y__h203;
wire [9 : 0] base__h66, offset__h67;
// value method wrap64_getOffset
assign wrap64_getOffset = x__h79 | addrLSB__h68 ;
// remaining internal signals
assign addrLSB__h68 = wrap64_getOffset_cap[113:82] & y__h203 ;
assign base__h66 =
{ wrap64_getOffset_cap[1:0], wrap64_getOffset_cap[17:10] } ;
assign offset__h67 = { 2'b0, wrap64_getOffset_cap[81:74] } - base__h66 ;
assign x__h204 = 32'hFFFFFFFF << wrap64_getOffset_cap[31:26] ;
assign x__h79 = x__h81 << wrap64_getOffset_cap[31:26] ;
assign x__h81 = { {22{offset__h67[9]}}, offset__h67 } ;
assign y__h203 = ~x__h204 ;
endmodule // module_wrap64_getOffset

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_getPerms O 31
// wrap64_getPerms_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap64_getPerms_cap -> wrap64_getPerms
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_getPerms(wrap64_getPerms_cap,
wrap64_getPerms);
// value method wrap64_getPerms
input [114 : 0] wrap64_getPerms_cap;
output [30 : 0] wrap64_getPerms;
// signals for module outputs
wire [30 : 0] wrap64_getPerms;
// value method wrap64_getPerms
assign wrap64_getPerms = { 19'd0, wrap64_getPerms_cap[73:62] } ;
endmodule // module_wrap64_getPerms

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_getSoftPerms O 16 const
// wrap64_getSoftPerms_cap I 115 unused
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_getSoftPerms(wrap64_getSoftPerms_cap,
wrap64_getSoftPerms);
// value method wrap64_getSoftPerms
input [114 : 0] wrap64_getSoftPerms_cap;
output [15 : 0] wrap64_getSoftPerms;
// signals for module outputs
wire [15 : 0] wrap64_getSoftPerms;
// value method wrap64_getSoftPerms
assign wrap64_getSoftPerms = 16'd0 ;
endmodule // module_wrap64_getSoftPerms

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_getTop O 33
// wrap64_getTop_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap64_getTop_cap -> wrap64_getTop
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_getTop(wrap64_getTop_cap,
wrap64_getTop);
// value method wrap64_getTop
input [114 : 0] wrap64_getTop_cap;
output [32 : 0] wrap64_getTop;
// signals for module outputs
wire [32 : 0] wrap64_getTop;
// remaining internal signals
wire [32 : 0] addTop__h64, result__h512, ret__h66;
wire [24 : 0] mask__h65;
wire [23 : 0] wrap64_getTop_cap_BITS_113_TO_90_PLUS_SEXT_wra_ETC__q2;
wire [9 : 0] x__h178;
wire [1 : 0] wrap64_getTop_cap_BITS_1_TO_0__q1;
// value method wrap64_getTop
assign wrap64_getTop =
(wrap64_getTop_cap[31:26] < 6'd25 &&
ret__h66[32:31] -
{ 1'b0,
(wrap64_getTop_cap[31:26] == 6'd24) ?
wrap64_getTop_cap[17] :
wrap64_getTop_cap_BITS_113_TO_90_PLUS_SEXT_wra_ETC__q2[23] } >
2'd1) ?
result__h512 :
ret__h66 ;
// remaining internal signals
assign addTop__h64 =
{ {23{x__h178[9]}}, x__h178 } << wrap64_getTop_cap[31:26] ;
assign mask__h65 = 25'd33554431 << wrap64_getTop_cap[31:26] ;
assign result__h512 = { ~ret__h66[32], ret__h66[31:0] } ;
assign ret__h66 =
{ { 1'b0, wrap64_getTop_cap[113:90] } & mask__h65, 8'd0 } +
addTop__h64 ;
assign wrap64_getTop_cap_BITS_113_TO_90_PLUS_SEXT_wra_ETC__q2 =
wrap64_getTop_cap[113:90] +
({ {22{wrap64_getTop_cap_BITS_1_TO_0__q1[1]}},
wrap64_getTop_cap_BITS_1_TO_0__q1 } <<
wrap64_getTop_cap[31:26]) ;
assign wrap64_getTop_cap_BITS_1_TO_0__q1 = wrap64_getTop_cap[1:0] ;
assign x__h178 = { wrap64_getTop_cap[3:2], wrap64_getTop_cap[25:18] } ;
endmodule // module_wrap64_getTop

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_incOffset O 116
// wrap64_incOffset_cap I 115
// wrap64_incOffset_inc I 32
//
// Combinational paths from inputs to outputs:
// (wrap64_incOffset_cap, wrap64_incOffset_inc) -> wrap64_incOffset
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_incOffset(wrap64_incOffset_cap,
wrap64_incOffset_inc,
wrap64_incOffset);
// value method wrap64_incOffset
input [114 : 0] wrap64_incOffset_cap;
input [31 : 0] wrap64_incOffset_inc;
output [115 : 0] wrap64_incOffset;
// signals for module outputs
wire [115 : 0] wrap64_incOffset;
// remaining internal signals
wire [31 : 0] result_d_address__h574, x__h488, x__h597;
wire [23 : 0] highBitsfilter__h79,
highOffsetBits__h80,
signBits__h77,
x__h107;
wire [7 : 0] repBoundBits__h86, toBoundsM1__h90, toBounds__h89;
wire [3 : 0] IF_wrap64_incOffset_cap_BITS_25_TO_23_9_ULT_wr_ETC___d53;
wire [2 : 0] repBound__h738;
wire IF_wrap64_incOffset_inc_BIT_31_THEN_NOT_wrap64_ETC___d23,
wrap64_incOffset_cap_BITS_113_TO_82_0_PLUS_wra_ETC___d43,
wrap64_incOffset_cap_BITS_17_TO_15_7_ULT_wrap6_ETC___d41,
wrap64_incOffset_cap_BITS_25_TO_23_9_ULT_wrap6_ETC___d40;
// value method wrap64_incOffset
assign wrap64_incOffset =
{ highOffsetBits__h80 == 24'd0 &&
IF_wrap64_incOffset_inc_BIT_31_THEN_NOT_wrap64_ETC___d23 ||
wrap64_incOffset_cap[31:26] >= 6'd24,
(highOffsetBits__h80 == 24'd0 &&
IF_wrap64_incOffset_inc_BIT_31_THEN_NOT_wrap64_ETC___d23 ||
wrap64_incOffset_cap[31:26] >= 6'd24) &&
wrap64_incOffset_cap[114],
result_d_address__h574,
x__h597[7:0],
wrap64_incOffset_cap[73:10],
repBound__h738,
wrap64_incOffset_cap_BITS_25_TO_23_9_ULT_wrap6_ETC___d40,
wrap64_incOffset_cap_BITS_17_TO_15_7_ULT_wrap6_ETC___d41,
wrap64_incOffset_cap_BITS_113_TO_82_0_PLUS_wra_ETC___d43,
IF_wrap64_incOffset_cap_BITS_25_TO_23_9_ULT_wr_ETC___d53 } ;
// remaining internal signals
assign IF_wrap64_incOffset_cap_BITS_25_TO_23_9_ULT_wr_ETC___d53 =
{ (wrap64_incOffset_cap_BITS_25_TO_23_9_ULT_wrap6_ETC___d40 ==
wrap64_incOffset_cap_BITS_113_TO_82_0_PLUS_wra_ETC___d43) ?
2'd0 :
((wrap64_incOffset_cap_BITS_25_TO_23_9_ULT_wrap6_ETC___d40 &&
!wrap64_incOffset_cap_BITS_113_TO_82_0_PLUS_wra_ETC___d43) ?
2'd1 :
2'd3),
(wrap64_incOffset_cap_BITS_17_TO_15_7_ULT_wrap6_ETC___d41 ==
wrap64_incOffset_cap_BITS_113_TO_82_0_PLUS_wra_ETC___d43) ?
2'd0 :
((wrap64_incOffset_cap_BITS_17_TO_15_7_ULT_wrap6_ETC___d41 &&
!wrap64_incOffset_cap_BITS_113_TO_82_0_PLUS_wra_ETC___d43) ?
2'd1 :
2'd3) } ;
assign IF_wrap64_incOffset_inc_BIT_31_THEN_NOT_wrap64_ETC___d23 =
wrap64_incOffset_inc[31] ?
x__h488[7:0] >= toBounds__h89 &&
repBoundBits__h86 != wrap64_incOffset_cap[81:74] :
x__h488[7:0] < toBoundsM1__h90 ;
assign highBitsfilter__h79 = 24'd16777215 << wrap64_incOffset_cap[31:26] ;
assign highOffsetBits__h80 = x__h107 & highBitsfilter__h79 ;
assign repBoundBits__h86 = { wrap64_incOffset_cap[9:7], 5'd0 } ;
assign repBound__h738 = wrap64_incOffset_cap[17:15] - 3'b001 ;
assign result_d_address__h574 =
wrap64_incOffset_cap[113:82] + wrap64_incOffset_inc ;
assign signBits__h77 = {24{wrap64_incOffset_inc[31]}} ;
assign toBoundsM1__h90 = repBoundBits__h86 + ~wrap64_incOffset_cap[81:74] ;
assign toBounds__h89 = repBoundBits__h86 - wrap64_incOffset_cap[81:74] ;
assign wrap64_incOffset_cap_BITS_113_TO_82_0_PLUS_wra_ETC___d43 =
x__h597[7:5] < repBound__h738 ;
assign wrap64_incOffset_cap_BITS_17_TO_15_7_ULT_wrap6_ETC___d41 =
wrap64_incOffset_cap[17:15] < repBound__h738 ;
assign wrap64_incOffset_cap_BITS_25_TO_23_9_ULT_wrap6_ETC___d40 =
wrap64_incOffset_cap[25:23] < repBound__h738 ;
assign x__h107 = wrap64_incOffset_inc[31:8] ^ signBits__h77 ;
assign x__h488 = wrap64_incOffset_inc >> wrap64_incOffset_cap[31:26] ;
assign x__h597 = result_d_address__h574 >> wrap64_incOffset_cap[31:26] ;
endmodule // module_wrap64_incOffset

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_isInBounds O 1
// wrap64_isInBounds_cap I 115
// wrap64_isInBounds_isTopIncluded I 1
//
// Combinational paths from inputs to outputs:
// (wrap64_isInBounds_cap,
// wrap64_isInBounds_isTopIncluded) -> wrap64_isInBounds
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_isInBounds(wrap64_isInBounds_cap,
wrap64_isInBounds_isTopIncluded,
wrap64_isInBounds);
// value method wrap64_isInBounds
input [114 : 0] wrap64_isInBounds_cap;
input wrap64_isInBounds_isTopIncluded;
output wrap64_isInBounds;
// signals for module outputs
wire wrap64_isInBounds;
// value method wrap64_isInBounds
assign wrap64_isInBounds =
((wrap64_isInBounds_cap[6] == wrap64_isInBounds_cap[4]) ?
(wrap64_isInBounds_isTopIncluded ?
wrap64_isInBounds_cap[81:74] <=
wrap64_isInBounds_cap[25:18] :
wrap64_isInBounds_cap[81:74] <
wrap64_isInBounds_cap[25:18]) :
wrap64_isInBounds_cap[6]) &&
((wrap64_isInBounds_cap[5] == wrap64_isInBounds_cap[4]) ?
wrap64_isInBounds_cap[81:74] >= wrap64_isInBounds_cap[17:10] :
wrap64_isInBounds_cap[4]) ;
endmodule // module_wrap64_isInBounds

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_isValidCap O 1
// wrap64_isValidCap_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap64_isValidCap_cap -> wrap64_isValidCap
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_isValidCap(wrap64_isValidCap_cap,
wrap64_isValidCap);
// value method wrap64_isValidCap
input [114 : 0] wrap64_isValidCap_cap;
output wrap64_isValidCap;
// signals for module outputs
wire wrap64_isValidCap;
// value method wrap64_isValidCap
assign wrap64_isValidCap = wrap64_isValidCap_cap[114] ;
endmodule // module_wrap64_isValidCap

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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_modifyOffset O 116
// wrap64_modifyOffset_cap I 115
// wrap64_modifyOffset_offset I 32
// wrap64_modifyOffset_doInc I 1
//
// Combinational paths from inputs to outputs:
// (wrap64_modifyOffset_cap,
// wrap64_modifyOffset_offset,
// wrap64_modifyOffset_doInc) -> wrap64_modifyOffset
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_modifyOffset(wrap64_modifyOffset_cap,
wrap64_modifyOffset_offset,
wrap64_modifyOffset_doInc,
wrap64_modifyOffset);
// value method wrap64_modifyOffset
input [114 : 0] wrap64_modifyOffset_cap;
input [31 : 0] wrap64_modifyOffset_offset;
input wrap64_modifyOffset_doInc;
output [115 : 0] wrap64_modifyOffset;
// signals for module outputs
wire [115 : 0] wrap64_modifyOffset;
// remaining internal signals
reg [1 : 0] mask__h585;
wire [31 : 0] addBase__h631,
pointer__h74,
result_d_address__h600,
ret___1_address__h611,
x__h491,
x__h741;
wire [23 : 0] highOffsetBits__h81, mask__h632, signBits__h78, x__h108;
wire [9 : 0] x__h682;
wire [7 : 0] newAddrBits__h584,
repBoundBits__h87,
result_d_addrBits__h601,
toBoundsM1_A__h86,
toBoundsM1_B__h89,
toBoundsM1__h91,
toBounds_A__h85,
toBounds_B__h88,
toBounds__h90;
wire [3 : 0] IF_wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_ETC___d83;
wire [2 : 0] repBound__h881;
wire IF_wrap64_modifyOffset_doInc_THEN_wrap64_modif_ETC___d73,
IF_wrap64_modifyOffset_offset_BIT_31_THEN_NOT__ETC___d34,
NOT_wrap64_modifyOffset_offset_SRL_wrap64_modi_ETC___d25,
wrap64_modifyOffset_cap_BITS_17_TO_15_7_ULT_wr_ETC___d71,
wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_wr_ETC___d70;
// value method wrap64_modifyOffset
assign wrap64_modifyOffset =
{ highOffsetBits__h81 == 24'd0 &&
IF_wrap64_modifyOffset_offset_BIT_31_THEN_NOT__ETC___d34 ||
wrap64_modifyOffset_cap[31:26] >= 6'd24,
(highOffsetBits__h81 == 24'd0 &&
IF_wrap64_modifyOffset_offset_BIT_31_THEN_NOT__ETC___d34 ||
wrap64_modifyOffset_cap[31:26] >= 6'd24) &&
wrap64_modifyOffset_cap[114],
result_d_address__h600,
result_d_addrBits__h601,
wrap64_modifyOffset_cap[73:10],
repBound__h881,
wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_wr_ETC___d70,
wrap64_modifyOffset_cap_BITS_17_TO_15_7_ULT_wr_ETC___d71,
IF_wrap64_modifyOffset_doInc_THEN_wrap64_modif_ETC___d73,
IF_wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_ETC___d83 } ;
// remaining internal signals
assign IF_wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_ETC___d83 =
{ (wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_wr_ETC___d70 ==
IF_wrap64_modifyOffset_doInc_THEN_wrap64_modif_ETC___d73) ?
2'd0 :
((wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_wr_ETC___d70 &&
!IF_wrap64_modifyOffset_doInc_THEN_wrap64_modif_ETC___d73) ?
2'd1 :
2'd3),
(wrap64_modifyOffset_cap_BITS_17_TO_15_7_ULT_wr_ETC___d71 ==
IF_wrap64_modifyOffset_doInc_THEN_wrap64_modif_ETC___d73) ?
2'd0 :
((wrap64_modifyOffset_cap_BITS_17_TO_15_7_ULT_wr_ETC___d71 &&
!IF_wrap64_modifyOffset_doInc_THEN_wrap64_modif_ETC___d73) ?
2'd1 :
2'd3) } ;
assign IF_wrap64_modifyOffset_doInc_THEN_wrap64_modif_ETC___d73 =
result_d_addrBits__h601[7:5] < repBound__h881 ;
assign IF_wrap64_modifyOffset_offset_BIT_31_THEN_NOT__ETC___d34 =
wrap64_modifyOffset_offset[31] ?
NOT_wrap64_modifyOffset_offset_SRL_wrap64_modi_ETC___d25 :
(wrap64_modifyOffset_doInc ?
x__h491[7:0] < toBoundsM1__h91 :
x__h491[7:0] <= toBoundsM1__h91) ;
assign NOT_wrap64_modifyOffset_offset_SRL_wrap64_modi_ETC___d25 =
x__h491[7:0] >= toBounds__h90 &&
(!wrap64_modifyOffset_doInc ||
repBoundBits__h87 != wrap64_modifyOffset_cap[81:74]) ;
assign addBase__h631 =
{ {22{x__h682[9]}}, x__h682 } << wrap64_modifyOffset_cap[31:26] ;
assign highOffsetBits__h81 = x__h108 & mask__h632 ;
assign mask__h632 = 24'd16777215 << wrap64_modifyOffset_cap[31:26] ;
assign newAddrBits__h584 = wrap64_modifyOffset_cap[17:10] + x__h491[7:0] ;
assign pointer__h74 =
wrap64_modifyOffset_cap[113:82] + wrap64_modifyOffset_offset ;
assign repBoundBits__h87 = { wrap64_modifyOffset_cap[9:7], 5'd0 } ;
assign repBound__h881 = wrap64_modifyOffset_cap[17:15] - 3'b001 ;
assign result_d_addrBits__h601 =
wrap64_modifyOffset_doInc ?
x__h741[7:0] :
{ mask__h585, 6'd63 } & newAddrBits__h584 ;
assign result_d_address__h600 =
wrap64_modifyOffset_doInc ?
pointer__h74 :
ret___1_address__h611 ;
assign ret___1_address__h611 =
{ wrap64_modifyOffset_cap[113:90] & mask__h632, 8'd0 } +
addBase__h631 +
wrap64_modifyOffset_offset ;
assign signBits__h78 = {24{wrap64_modifyOffset_offset[31]}} ;
assign toBoundsM1_A__h86 = { 3'b110, ~wrap64_modifyOffset_cap[14:10] } ;
assign toBoundsM1_B__h89 =
repBoundBits__h87 + ~wrap64_modifyOffset_cap[81:74] ;
assign toBoundsM1__h91 =
wrap64_modifyOffset_doInc ?
toBoundsM1_B__h89 :
toBoundsM1_A__h86 ;
assign toBounds_A__h85 = 8'd224 - { 3'b0, wrap64_modifyOffset_cap[14:10] } ;
assign toBounds_B__h88 =
repBoundBits__h87 - wrap64_modifyOffset_cap[81:74] ;
assign toBounds__h90 =
wrap64_modifyOffset_doInc ? toBounds_B__h88 : toBounds_A__h85 ;
assign wrap64_modifyOffset_cap_BITS_17_TO_15_7_ULT_wr_ETC___d71 =
wrap64_modifyOffset_cap[17:15] < repBound__h881 ;
assign wrap64_modifyOffset_cap_BITS_25_TO_23_9_ULT_wr_ETC___d70 =
wrap64_modifyOffset_cap[25:23] < repBound__h881 ;
assign x__h108 = wrap64_modifyOffset_offset[31:8] ^ signBits__h78 ;
assign x__h491 =
wrap64_modifyOffset_offset >> wrap64_modifyOffset_cap[31:26] ;
assign x__h682 =
{ wrap64_modifyOffset_cap[1:0],
wrap64_modifyOffset_cap[17:10] } ;
assign x__h741 = pointer__h74 >> wrap64_modifyOffset_cap[31:26] ;
always@(wrap64_modifyOffset_cap)
begin
case (wrap64_modifyOffset_cap[31:26])
6'd25: mask__h585 = 2'b01;
6'd26: mask__h585 = 2'b0;
default: mask__h585 = 2'b11;
endcase
end
endmodule // module_wrap64_modifyOffset

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module_wrap64_nullCap.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:26 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_nullCap O 115 const
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_nullCap(wrap64_nullCap);
// value method wrap64_nullCap
output [114 : 0] wrap64_nullCap;
// signals for module outputs
wire [114 : 0] wrap64_nullCap;
// value method wrap64_nullCap
assign wrap64_nullCap = 115'h00000000000001F555555690003F0 ;
endmodule // module_wrap64_nullCap

52
module_wrap64_nullWithAddr.v Normal file
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@@ -0,0 +1,52 @@
//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:26 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_nullWithAddr O 115
// wrap64_nullWithAddr_addr I 32
//
// Combinational paths from inputs to outputs:
// wrap64_nullWithAddr_addr -> wrap64_nullWithAddr
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_nullWithAddr(wrap64_nullWithAddr_addr,
wrap64_nullWithAddr);
// value method wrap64_nullWithAddr
input [31 : 0] wrap64_nullWithAddr_addr;
output [114 : 0] wrap64_nullWithAddr;
// signals for module outputs
wire [114 : 0] wrap64_nullWithAddr;
// remaining internal signals
wire [7 : 0] res_addrBits__h116;
// value method wrap64_nullWithAddr
assign wrap64_nullWithAddr =
{ 1'd0,
wrap64_nullWithAddr_addr,
res_addrBits__h116,
74'h0001F555555690003F0 } ;
// remaining internal signals
assign res_addrBits__h116 = { 2'd0, wrap64_nullWithAddr_addr[31:26] } ;
endmodule // module_wrap64_nullWithAddr

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module_wrap64_setAddr.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_setAddr O 116
// wrap64_setAddr_cap I 115
// wrap64_setAddr_addr I 32
//
// Combinational paths from inputs to outputs:
// (wrap64_setAddr_cap, wrap64_setAddr_addr) -> wrap64_setAddr
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_setAddr(wrap64_setAddr_cap,
wrap64_setAddr_addr,
wrap64_setAddr);
// value method wrap64_setAddr
input [114 : 0] wrap64_setAddr_cap;
input [31 : 0] wrap64_setAddr_addr;
output [115 : 0] wrap64_setAddr;
// signals for module outputs
wire [115 : 0] wrap64_setAddr;
// remaining internal signals
wire [31 : 0] x__h102;
wire [23 : 0] deltaAddrHi__h76, deltaAddrUpper__h78, mask__h77;
wire [3 : 0] IF_wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap_ETC___d40;
wire [2 : 0] repBound__h430;
wire [1 : 0] x__h84;
wire SEXT__0b0_CONCAT_wrap64_setAddr_addr_SRL_wrap6_ETC___d18,
wrap64_setAddr_addr_SRL_wrap64_setAddr_cap_BIT_ETC___d30,
wrap64_setAddr_cap_BITS_17_TO_15_5_ULT_wrap64__ETC___d29,
wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap64__ETC___d28;
// value method wrap64_setAddr
assign wrap64_setAddr =
{ SEXT__0b0_CONCAT_wrap64_setAddr_addr_SRL_wrap6_ETC___d18,
SEXT__0b0_CONCAT_wrap64_setAddr_addr_SRL_wrap6_ETC___d18 &&
wrap64_setAddr_cap[114],
wrap64_setAddr_addr,
x__h102[7:0],
wrap64_setAddr_cap[73:10],
repBound__h430,
wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap64__ETC___d28,
wrap64_setAddr_cap_BITS_17_TO_15_5_ULT_wrap64__ETC___d29,
wrap64_setAddr_addr_SRL_wrap64_setAddr_cap_BIT_ETC___d30,
IF_wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap_ETC___d40 } ;
// remaining internal signals
assign IF_wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap_ETC___d40 =
{ (wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap64__ETC___d28 ==
wrap64_setAddr_addr_SRL_wrap64_setAddr_cap_BIT_ETC___d30) ?
2'd0 :
((wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap64__ETC___d28 &&
!wrap64_setAddr_addr_SRL_wrap64_setAddr_cap_BIT_ETC___d30) ?
2'd1 :
2'd3),
(wrap64_setAddr_cap_BITS_17_TO_15_5_ULT_wrap64__ETC___d29 ==
wrap64_setAddr_addr_SRL_wrap64_setAddr_cap_BIT_ETC___d30) ?
2'd0 :
((wrap64_setAddr_cap_BITS_17_TO_15_5_ULT_wrap64__ETC___d29 &&
!wrap64_setAddr_addr_SRL_wrap64_setAddr_cap_BIT_ETC___d30) ?
2'd1 :
2'd3) } ;
assign SEXT__0b0_CONCAT_wrap64_setAddr_addr_SRL_wrap6_ETC___d18 =
deltaAddrHi__h76 == deltaAddrUpper__h78 ;
assign deltaAddrHi__h76 =
{ {22{x__h84[1]}}, x__h84 } << wrap64_setAddr_cap[31:26] ;
assign deltaAddrUpper__h78 =
(wrap64_setAddr_addr[31:8] & mask__h77) -
(wrap64_setAddr_cap[113:90] & mask__h77) ;
assign mask__h77 = 24'd16777215 << wrap64_setAddr_cap[31:26] ;
assign repBound__h430 = wrap64_setAddr_cap[17:15] - 3'b001 ;
assign wrap64_setAddr_addr_SRL_wrap64_setAddr_cap_BIT_ETC___d30 =
x__h102[7:5] < repBound__h430 ;
assign wrap64_setAddr_cap_BITS_17_TO_15_5_ULT_wrap64__ETC___d29 =
wrap64_setAddr_cap[17:15] < repBound__h430 ;
assign wrap64_setAddr_cap_BITS_25_TO_23_7_ULT_wrap64__ETC___d28 =
wrap64_setAddr_cap[25:23] < repBound__h430 ;
assign x__h102 = wrap64_setAddr_addr >> wrap64_setAddr_cap[31:26] ;
assign x__h84 =
{ 1'b0, x__h102[7:5] < wrap64_setAddr_cap[9:7] } -
{ 1'b0, wrap64_setAddr_cap[4] } ;
endmodule // module_wrap64_setAddr

558
module_wrap64_setBounds.v Normal file
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@@ -0,0 +1,558 @@
//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_setBounds O 116
// wrap64_setBounds_cap I 115
// wrap64_setBounds_length I 32
//
// Combinational paths from inputs to outputs:
// (wrap64_setBounds_cap, wrap64_setBounds_length) -> wrap64_setBounds
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_setBounds(wrap64_setBounds_cap,
wrap64_setBounds_length,
wrap64_setBounds);
// value method wrap64_setBounds
input [114 : 0] wrap64_setBounds_cap;
input [31 : 0] wrap64_setBounds_length;
output [115 : 0] wrap64_setBounds;
// signals for module outputs
wire [115 : 0] wrap64_setBounds;
// remaining internal signals
wire [33 : 0] base__h84,
len__h86,
lmaskLo__h92,
lmaskLor__h91,
mwLsbMask__h100,
top__h87,
x__h4494,
x__h4615,
x__h4798,
y__h4495;
wire [31 : 0] wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d110,
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d10,
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d13,
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d16,
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d4,
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d7;
wire [15 : 0] IF_NOT_wrap64_setBounds_length_BIT_31_1_2_AND__ETC___d212;
wire [8 : 0] x__h4837;
wire [7 : 0] _theResult_____3_fst_bounds_topBits__h4604,
result_cap_addrBits__h4434,
ret_bounds_baseBits__h4780,
ret_bounds_topBits__h4600,
ret_bounds_topBits__h4829,
x__h4874,
x__h4877;
wire [5 : 0] IF_wrap64_setBounds_length_AND_15_CONCAT_INV_w_ETC___d190,
_25_MINUS_0_CONCAT_IF_wrap64_setBounds_length_B_ETC___d183;
wire [3 : 0] IF_IF_NOT_wrap64_setBounds_length_BIT_31_1_2_A_ETC___d234;
wire [2 : 0] repBound__h4867;
wire IF_NOT_wrap64_setBounds_length_BIT_31_1_2_AND__ETC___d221,
IF_NOT_wrap64_setBounds_length_BIT_31_1_2_AND__ETC___d222,
IF_wrap64_setBounds_length_AND_15_CONCAT_INV_w_ETC___d224,
NOT_0_CONCAT_wrap64_setBounds_length_OR_0_CONC_ETC___d122,
NOT_0b0_CONCAT_wrap64_setBounds_cap_BITS_113_T_ETC___d191,
NOT_0b0_CONCAT_wrap64_setBounds_cap_BITS_113_T_ETC___d202,
_0b0_CONCAT_wrap64_setBounds_cap_BITS_113_TO_82_ETC___d105,
wrap64_setBounds_cap_BITS_113_TO_82_AND_0_CONC_ETC___d98,
wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d123,
wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d129,
wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d130;
// value method wrap64_setBounds
assign wrap64_setBounds =
{ wrap64_setBounds_cap_BITS_113_TO_82_AND_0_CONC_ETC___d98 &&
_0b0_CONCAT_wrap64_setBounds_cap_BITS_113_TO_82_ETC___d105,
wrap64_setBounds_cap[114:82],
result_cap_addrBits__h4434,
wrap64_setBounds_cap[73:33],
wrap64_setBounds_length[31] || wrap64_setBounds_length[30] ||
wrap64_setBounds_length[29] ||
wrap64_setBounds_length[28] ||
wrap64_setBounds_length[27] ||
wrap64_setBounds_length[26] ||
wrap64_setBounds_length[25] ||
wrap64_setBounds_length[24] ||
wrap64_setBounds_length[23] ||
wrap64_setBounds_length[22] ||
wrap64_setBounds_length[21] ||
wrap64_setBounds_length[20] ||
wrap64_setBounds_length[19] ||
wrap64_setBounds_length[18] ||
wrap64_setBounds_length[17] ||
wrap64_setBounds_length[16] ||
wrap64_setBounds_length[15] ||
wrap64_setBounds_length[14] ||
wrap64_setBounds_length[13] ||
wrap64_setBounds_length[12] ||
wrap64_setBounds_length[11] ||
wrap64_setBounds_length[10] ||
wrap64_setBounds_length[9] ||
wrap64_setBounds_length[8] ||
wrap64_setBounds_length[7] ||
wrap64_setBounds_length[6],
IF_wrap64_setBounds_length_AND_15_CONCAT_INV_w_ETC___d190,
IF_NOT_wrap64_setBounds_length_BIT_31_1_2_AND__ETC___d212,
repBound__h4867,
IF_NOT_wrap64_setBounds_length_BIT_31_1_2_AND__ETC___d221,
IF_NOT_wrap64_setBounds_length_BIT_31_1_2_AND__ETC___d222,
IF_wrap64_setBounds_length_AND_15_CONCAT_INV_w_ETC___d224,
IF_IF_NOT_wrap64_setBounds_length_BIT_31_1_2_A_ETC___d234 } ;
// remaining internal signals
assign IF_IF_NOT_wrap64_setBounds_length_BIT_31_1_2_A_ETC___d234 =
{ (IF_NOT_wrap64_setBounds_length_BIT_31_1_2_AND__ETC___d221 ==
IF_wrap64_setBounds_length_AND_15_CONCAT_INV_w_ETC___d224) ?
2'd0 :
((IF_NOT_wrap64_setBounds_length_BIT_31_1_2_AND__ETC___d221 &&
!IF_wrap64_setBounds_length_AND_15_CONCAT_INV_w_ETC___d224) ?
2'd1 :
2'd3),
(IF_NOT_wrap64_setBounds_length_BIT_31_1_2_AND__ETC___d222 ==
IF_wrap64_setBounds_length_AND_15_CONCAT_INV_w_ETC___d224) ?
2'd0 :
((IF_NOT_wrap64_setBounds_length_BIT_31_1_2_AND__ETC___d222 &&
!IF_wrap64_setBounds_length_AND_15_CONCAT_INV_w_ETC___d224) ?
2'd1 :
2'd3) } ;
assign IF_NOT_wrap64_setBounds_length_BIT_31_1_2_AND__ETC___d212 =
(!wrap64_setBounds_length[31] && !wrap64_setBounds_length[30] &&
!wrap64_setBounds_length[29] &&
!wrap64_setBounds_length[28] &&
!wrap64_setBounds_length[27] &&
!wrap64_setBounds_length[26] &&
!wrap64_setBounds_length[25] &&
!wrap64_setBounds_length[24] &&
!wrap64_setBounds_length[23] &&
!wrap64_setBounds_length[22] &&
!wrap64_setBounds_length[21] &&
!wrap64_setBounds_length[20] &&
!wrap64_setBounds_length[19] &&
!wrap64_setBounds_length[18] &&
!wrap64_setBounds_length[17] &&
!wrap64_setBounds_length[16] &&
!wrap64_setBounds_length[15] &&
!wrap64_setBounds_length[14] &&
!wrap64_setBounds_length[13] &&
!wrap64_setBounds_length[12] &&
!wrap64_setBounds_length[11] &&
!wrap64_setBounds_length[10] &&
!wrap64_setBounds_length[9] &&
!wrap64_setBounds_length[8] &&
!wrap64_setBounds_length[7] &&
!wrap64_setBounds_length[6]) ?
{ ret_bounds_topBits__h4829, x__h4615[7:0] } :
{ ret_bounds_topBits__h4600[7:3],
3'd0,
ret_bounds_baseBits__h4780 } ;
assign IF_NOT_wrap64_setBounds_length_BIT_31_1_2_AND__ETC___d221 =
x__h4877[7:5] < repBound__h4867 ;
assign IF_NOT_wrap64_setBounds_length_BIT_31_1_2_AND__ETC___d222 =
x__h4874[7:5] < repBound__h4867 ;
assign IF_wrap64_setBounds_length_AND_15_CONCAT_INV_w_ETC___d190 =
(wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d130 &&
(wrap64_setBounds_length[31] || wrap64_setBounds_length[30] ||
wrap64_setBounds_length[29] ||
wrap64_setBounds_length[28] ||
wrap64_setBounds_length[27] ||
wrap64_setBounds_length[26] ||
wrap64_setBounds_length[25] ||
wrap64_setBounds_length[24] ||
wrap64_setBounds_length[23] ||
wrap64_setBounds_length[22] ||
wrap64_setBounds_length[21] ||
wrap64_setBounds_length[20] ||
wrap64_setBounds_length[19] ||
wrap64_setBounds_length[18] ||
wrap64_setBounds_length[17] ||
wrap64_setBounds_length[16] ||
wrap64_setBounds_length[15] ||
wrap64_setBounds_length[14] ||
wrap64_setBounds_length[13] ||
wrap64_setBounds_length[12] ||
wrap64_setBounds_length[11] ||
wrap64_setBounds_length[10] ||
wrap64_setBounds_length[9] ||
wrap64_setBounds_length[8] ||
wrap64_setBounds_length[7] ||
wrap64_setBounds_length[6])) ?
_25_MINUS_0_CONCAT_IF_wrap64_setBounds_length_B_ETC___d183 +
6'd1 :
_25_MINUS_0_CONCAT_IF_wrap64_setBounds_length_B_ETC___d183 ;
assign IF_wrap64_setBounds_length_AND_15_CONCAT_INV_w_ETC___d224 =
result_cap_addrBits__h4434[7:5] < repBound__h4867 ;
assign NOT_0_CONCAT_wrap64_setBounds_length_OR_0_CONC_ETC___d122 =
(mwLsbMask__h100 & top__h87) != (x__h4494 ^ y__h4495) ;
assign NOT_0b0_CONCAT_wrap64_setBounds_cap_BITS_113_T_ETC___d191 =
(top__h87 & lmaskLor__h91) != 34'd0 &&
(wrap64_setBounds_length[31] || wrap64_setBounds_length[30] ||
wrap64_setBounds_length[29] ||
wrap64_setBounds_length[28] ||
wrap64_setBounds_length[27] ||
wrap64_setBounds_length[26] ||
wrap64_setBounds_length[25] ||
wrap64_setBounds_length[24] ||
wrap64_setBounds_length[23] ||
wrap64_setBounds_length[22] ||
wrap64_setBounds_length[21] ||
wrap64_setBounds_length[20] ||
wrap64_setBounds_length[19] ||
wrap64_setBounds_length[18] ||
wrap64_setBounds_length[17] ||
wrap64_setBounds_length[16] ||
wrap64_setBounds_length[15] ||
wrap64_setBounds_length[14] ||
wrap64_setBounds_length[13] ||
wrap64_setBounds_length[12] ||
wrap64_setBounds_length[11] ||
wrap64_setBounds_length[10] ||
wrap64_setBounds_length[9] ||
wrap64_setBounds_length[8] ||
wrap64_setBounds_length[7] ||
wrap64_setBounds_length[6]) ;
assign NOT_0b0_CONCAT_wrap64_setBounds_cap_BITS_113_T_ETC___d202 =
(top__h87 & lmaskLo__h92) != 34'd0 &&
(wrap64_setBounds_length[31] || wrap64_setBounds_length[30] ||
wrap64_setBounds_length[29] ||
wrap64_setBounds_length[28] ||
wrap64_setBounds_length[27] ||
wrap64_setBounds_length[26] ||
wrap64_setBounds_length[25] ||
wrap64_setBounds_length[24] ||
wrap64_setBounds_length[23] ||
wrap64_setBounds_length[22] ||
wrap64_setBounds_length[21] ||
wrap64_setBounds_length[20] ||
wrap64_setBounds_length[19] ||
wrap64_setBounds_length[18] ||
wrap64_setBounds_length[17] ||
wrap64_setBounds_length[16] ||
wrap64_setBounds_length[15] ||
wrap64_setBounds_length[14] ||
wrap64_setBounds_length[13] ||
wrap64_setBounds_length[12] ||
wrap64_setBounds_length[11] ||
wrap64_setBounds_length[10] ||
wrap64_setBounds_length[9] ||
wrap64_setBounds_length[8] ||
wrap64_setBounds_length[7] ||
wrap64_setBounds_length[6]) ;
assign _0b0_CONCAT_wrap64_setBounds_cap_BITS_113_TO_82_ETC___d105 =
(top__h87 & lmaskLor__h91) == 34'd0 ||
!wrap64_setBounds_length[31] && !wrap64_setBounds_length[30] &&
!wrap64_setBounds_length[29] &&
!wrap64_setBounds_length[28] &&
!wrap64_setBounds_length[27] &&
!wrap64_setBounds_length[26] &&
!wrap64_setBounds_length[25] &&
!wrap64_setBounds_length[24] &&
!wrap64_setBounds_length[23] &&
!wrap64_setBounds_length[22] &&
!wrap64_setBounds_length[21] &&
!wrap64_setBounds_length[20] &&
!wrap64_setBounds_length[19] &&
!wrap64_setBounds_length[18] &&
!wrap64_setBounds_length[17] &&
!wrap64_setBounds_length[16] &&
!wrap64_setBounds_length[15] &&
!wrap64_setBounds_length[14] &&
!wrap64_setBounds_length[13] &&
!wrap64_setBounds_length[12] &&
!wrap64_setBounds_length[11] &&
!wrap64_setBounds_length[10] &&
!wrap64_setBounds_length[9] &&
!wrap64_setBounds_length[8] &&
!wrap64_setBounds_length[7] &&
!wrap64_setBounds_length[6] ;
assign _25_MINUS_0_CONCAT_IF_wrap64_setBounds_length_B_ETC___d183 =
6'd25 -
{ 1'd0,
wrap64_setBounds_length[31] ?
5'd0 :
(wrap64_setBounds_length[30] ?
5'd1 :
(wrap64_setBounds_length[29] ?
5'd2 :
(wrap64_setBounds_length[28] ?
5'd3 :
(wrap64_setBounds_length[27] ?
5'd4 :
(wrap64_setBounds_length[26] ?
5'd5 :
(wrap64_setBounds_length[25] ?
5'd6 :
(wrap64_setBounds_length[24] ?
5'd7 :
(wrap64_setBounds_length[23] ?
5'd8 :
(wrap64_setBounds_length[22] ?
5'd9 :
(wrap64_setBounds_length[21] ?
5'd10 :
(wrap64_setBounds_length[20] ?
5'd11 :
(wrap64_setBounds_length[19] ?
5'd12 :
(wrap64_setBounds_length[18] ?
5'd13 :
(wrap64_setBounds_length[17] ?
5'd14 :
(wrap64_setBounds_length[16] ?
5'd15 :
(wrap64_setBounds_length[15] ?
5'd16 :
(wrap64_setBounds_length[14] ?
5'd17 :
(wrap64_setBounds_length[13] ?
5'd18 :
(wrap64_setBounds_length[12] ?
5'd19 :
(wrap64_setBounds_length[11] ?
5'd20 :
(wrap64_setBounds_length[10] ?
5'd21 :
(wrap64_setBounds_length[9] ?
5'd22 :
(wrap64_setBounds_length[8] ?
5'd23 :
(wrap64_setBounds_length[7] ?
5'd24 :
5'd25)))))))))))))))))))))))) } ;
assign _theResult_____3_fst_bounds_topBits__h4604 =
NOT_0b0_CONCAT_wrap64_setBounds_cap_BITS_113_T_ETC___d202 ?
x__h4798[8:1] + 8'b00001000 :
x__h4798[8:1] ;
assign base__h84 = { 2'b0, wrap64_setBounds_cap[113:82] } ;
assign len__h86 = { 2'b0, wrap64_setBounds_length } ;
assign lmaskLo__h92 =
{ 5'd0,
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d16[31:3] } ;
assign lmaskLor__h91 =
{ 6'd0,
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d16[31:4] } ;
assign mwLsbMask__h100 = lmaskLor__h91 ^ lmaskLo__h92 ;
assign repBound__h4867 = x__h4874[7:5] - 3'b001 ;
assign result_cap_addrBits__h4434 =
(wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d130 &&
(wrap64_setBounds_length[31] || wrap64_setBounds_length[30] ||
wrap64_setBounds_length[29] ||
wrap64_setBounds_length[28] ||
wrap64_setBounds_length[27] ||
wrap64_setBounds_length[26] ||
wrap64_setBounds_length[25] ||
wrap64_setBounds_length[24] ||
wrap64_setBounds_length[23] ||
wrap64_setBounds_length[22] ||
wrap64_setBounds_length[21] ||
wrap64_setBounds_length[20] ||
wrap64_setBounds_length[19] ||
wrap64_setBounds_length[18] ||
wrap64_setBounds_length[17] ||
wrap64_setBounds_length[16] ||
wrap64_setBounds_length[15] ||
wrap64_setBounds_length[14] ||
wrap64_setBounds_length[13] ||
wrap64_setBounds_length[12] ||
wrap64_setBounds_length[11] ||
wrap64_setBounds_length[10] ||
wrap64_setBounds_length[9] ||
wrap64_setBounds_length[8] ||
wrap64_setBounds_length[7] ||
wrap64_setBounds_length[6])) ?
x__h4615[8:1] :
x__h4615[7:0] ;
assign ret_bounds_baseBits__h4780 =
{ result_cap_addrBits__h4434[7:3], 3'd0 } ;
assign ret_bounds_topBits__h4600 =
(wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d130 &&
(wrap64_setBounds_length[31] || wrap64_setBounds_length[30] ||
wrap64_setBounds_length[29] ||
wrap64_setBounds_length[28] ||
wrap64_setBounds_length[27] ||
wrap64_setBounds_length[26] ||
wrap64_setBounds_length[25] ||
wrap64_setBounds_length[24] ||
wrap64_setBounds_length[23] ||
wrap64_setBounds_length[22] ||
wrap64_setBounds_length[21] ||
wrap64_setBounds_length[20] ||
wrap64_setBounds_length[19] ||
wrap64_setBounds_length[18] ||
wrap64_setBounds_length[17] ||
wrap64_setBounds_length[16] ||
wrap64_setBounds_length[15] ||
wrap64_setBounds_length[14] ||
wrap64_setBounds_length[13] ||
wrap64_setBounds_length[12] ||
wrap64_setBounds_length[11] ||
wrap64_setBounds_length[10] ||
wrap64_setBounds_length[9] ||
wrap64_setBounds_length[8] ||
wrap64_setBounds_length[7] ||
wrap64_setBounds_length[6])) ?
_theResult_____3_fst_bounds_topBits__h4604 :
ret_bounds_topBits__h4829 ;
assign ret_bounds_topBits__h4829 =
NOT_0b0_CONCAT_wrap64_setBounds_cap_BITS_113_T_ETC___d191 ?
x__h4837[7:0] :
x__h4798[7:0] ;
assign top__h87 = base__h84 + len__h86 ;
assign wrap64_setBounds_cap_BITS_113_TO_82_AND_0_CONC_ETC___d98 =
(wrap64_setBounds_cap[113:82] &
{ 4'd0,
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d16[31:4] }) ==
32'd0 ||
!wrap64_setBounds_length[31] && !wrap64_setBounds_length[30] &&
!wrap64_setBounds_length[29] &&
!wrap64_setBounds_length[28] &&
!wrap64_setBounds_length[27] &&
!wrap64_setBounds_length[26] &&
!wrap64_setBounds_length[25] &&
!wrap64_setBounds_length[24] &&
!wrap64_setBounds_length[23] &&
!wrap64_setBounds_length[22] &&
!wrap64_setBounds_length[21] &&
!wrap64_setBounds_length[20] &&
!wrap64_setBounds_length[19] &&
!wrap64_setBounds_length[18] &&
!wrap64_setBounds_length[17] &&
!wrap64_setBounds_length[16] &&
!wrap64_setBounds_length[15] &&
!wrap64_setBounds_length[14] &&
!wrap64_setBounds_length[13] &&
!wrap64_setBounds_length[12] &&
!wrap64_setBounds_length[11] &&
!wrap64_setBounds_length[10] &&
!wrap64_setBounds_length[9] &&
!wrap64_setBounds_length[8] &&
!wrap64_setBounds_length[7] &&
!wrap64_setBounds_length[6] ;
assign wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d110 =
wrap64_setBounds_length &
{ 4'd15,
~wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d16[31:4] } ;
assign wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d123 =
wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d110 ==
(wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d16 ^
{ 3'd0,
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d16[31:3] }) &&
NOT_0_CONCAT_wrap64_setBounds_length_OR_0_CONC_ETC___d122 ;
assign wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d129 =
wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d110 ==
(wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d16 ^
{ 4'd0,
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d16[31:4] }) &&
(NOT_0_CONCAT_wrap64_setBounds_length_OR_0_CONC_ETC___d122 ||
(top__h87 & lmaskLor__h91) != 34'd0) ;
assign wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d130 =
wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d123 &&
(top__h87 & lmaskLor__h91) != 34'd0 ||
wrap64_setBounds_length_AND_15_CONCAT_INV_wrap_ETC___d129 ;
assign wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d10 =
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d7 |
{ 4'd0,
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d7[31:4] } ;
assign wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d13 =
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d10 |
{ 8'd0,
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d10[31:8] } ;
assign wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d16 =
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d13 |
{ 16'd0,
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d13[31:16] } ;
assign wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d4 =
wrap64_setBounds_length |
{ 1'd0, wrap64_setBounds_length[31:1] } ;
assign wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d7 =
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d4 |
{ 2'd0,
wrap64_setBounds_length_OR_0_CONCAT_wrap64_set_ETC___d4[31:2] } ;
assign x__h4494 = mwLsbMask__h100 & base__h84 ;
assign x__h4615 =
base__h84 >>
_25_MINUS_0_CONCAT_IF_wrap64_setBounds_length_B_ETC___d183 ;
assign x__h4798 =
top__h87 >>
_25_MINUS_0_CONCAT_IF_wrap64_setBounds_length_B_ETC___d183 ;
assign x__h4837 = x__h4798[8:0] + 9'b000001000 ;
assign x__h4874 =
(!wrap64_setBounds_length[31] && !wrap64_setBounds_length[30] &&
!wrap64_setBounds_length[29] &&
!wrap64_setBounds_length[28] &&
!wrap64_setBounds_length[27] &&
!wrap64_setBounds_length[26] &&
!wrap64_setBounds_length[25] &&
!wrap64_setBounds_length[24] &&
!wrap64_setBounds_length[23] &&
!wrap64_setBounds_length[22] &&
!wrap64_setBounds_length[21] &&
!wrap64_setBounds_length[20] &&
!wrap64_setBounds_length[19] &&
!wrap64_setBounds_length[18] &&
!wrap64_setBounds_length[17] &&
!wrap64_setBounds_length[16] &&
!wrap64_setBounds_length[15] &&
!wrap64_setBounds_length[14] &&
!wrap64_setBounds_length[13] &&
!wrap64_setBounds_length[12] &&
!wrap64_setBounds_length[11] &&
!wrap64_setBounds_length[10] &&
!wrap64_setBounds_length[9] &&
!wrap64_setBounds_length[8] &&
!wrap64_setBounds_length[7] &&
!wrap64_setBounds_length[6]) ?
result_cap_addrBits__h4434 :
ret_bounds_baseBits__h4780 ;
assign x__h4877 =
(!wrap64_setBounds_length[31] && !wrap64_setBounds_length[30] &&
!wrap64_setBounds_length[29] &&
!wrap64_setBounds_length[28] &&
!wrap64_setBounds_length[27] &&
!wrap64_setBounds_length[26] &&
!wrap64_setBounds_length[25] &&
!wrap64_setBounds_length[24] &&
!wrap64_setBounds_length[23] &&
!wrap64_setBounds_length[22] &&
!wrap64_setBounds_length[21] &&
!wrap64_setBounds_length[20] &&
!wrap64_setBounds_length[19] &&
!wrap64_setBounds_length[18] &&
!wrap64_setBounds_length[17] &&
!wrap64_setBounds_length[16] &&
!wrap64_setBounds_length[15] &&
!wrap64_setBounds_length[14] &&
!wrap64_setBounds_length[13] &&
!wrap64_setBounds_length[12] &&
!wrap64_setBounds_length[11] &&
!wrap64_setBounds_length[10] &&
!wrap64_setBounds_length[9] &&
!wrap64_setBounds_length[8] &&
!wrap64_setBounds_length[7] &&
!wrap64_setBounds_length[6]) ?
ret_bounds_topBits__h4600 :
{ ret_bounds_topBits__h4600[7:3], 3'd0 } ;
assign y__h4495 = mwLsbMask__h100 & len__h86 ;
endmodule // module_wrap64_setBounds

48
module_wrap64_setFlags.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_setFlags O 115
// wrap64_setFlags_cap I 115
// wrap64_setFlags_flags I 1
//
// Combinational paths from inputs to outputs:
// (wrap64_setFlags_cap, wrap64_setFlags_flags) -> wrap64_setFlags
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_setFlags(wrap64_setFlags_cap,
wrap64_setFlags_flags,
wrap64_setFlags);
// value method wrap64_setFlags
input [114 : 0] wrap64_setFlags_cap;
input wrap64_setFlags_flags;
output [114 : 0] wrap64_setFlags;
// signals for module outputs
wire [114 : 0] wrap64_setFlags;
// value method wrap64_setFlags
assign wrap64_setFlags =
{ wrap64_setFlags_cap[114:62],
wrap64_setFlags_flags,
wrap64_setFlags_cap[60:0] } ;
endmodule // module_wrap64_setFlags

49
module_wrap64_setHardPerms.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_setHardPerms O 115
// wrap64_setHardPerms_cap I 115
// wrap64_setHardPerms_hardperms I 12
//
// Combinational paths from inputs to outputs:
// (wrap64_setHardPerms_cap,
// wrap64_setHardPerms_hardperms) -> wrap64_setHardPerms
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_setHardPerms(wrap64_setHardPerms_cap,
wrap64_setHardPerms_hardperms,
wrap64_setHardPerms);
// value method wrap64_setHardPerms
input [114 : 0] wrap64_setHardPerms_cap;
input [11 : 0] wrap64_setHardPerms_hardperms;
output [114 : 0] wrap64_setHardPerms;
// signals for module outputs
wire [114 : 0] wrap64_setHardPerms;
// value method wrap64_setHardPerms
assign wrap64_setHardPerms =
{ wrap64_setHardPerms_cap[114:74],
wrap64_setHardPerms_hardperms,
wrap64_setHardPerms_cap[61:0] } ;
endmodule // module_wrap64_setHardPerms

64
module_wrap64_setKind.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_setKind O 115
// wrap64_setKind_cap I 115
// wrap64_setKind_kind I 7
//
// Combinational paths from inputs to outputs:
// (wrap64_setKind_cap, wrap64_setKind_kind) -> wrap64_setKind
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_setKind(wrap64_setKind_cap,
wrap64_setKind_kind,
wrap64_setKind);
// value method wrap64_setKind
input [114 : 0] wrap64_setKind_cap;
input [6 : 0] wrap64_setKind_kind;
output [114 : 0] wrap64_setKind;
// signals for module outputs
wire [114 : 0] wrap64_setKind;
// remaining internal signals
reg [3 : 0] CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1;
// value method wrap64_setKind
assign wrap64_setKind =
{ wrap64_setKind_cap[114:61],
CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1,
wrap64_setKind_cap[56:0] } ;
// remaining internal signals
always@(wrap64_setKind_kind)
begin
case (wrap64_setKind_kind[6:4])
3'd0: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 = 4'd15;
3'd1: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 = 4'd14;
3'd2: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 = 4'd13;
3'd3: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 = 4'd12;
default: CASE_wrap64_setKind_kind_BITS_6_TO_4_0_15_1_14_ETC__q1 =
wrap64_setKind_kind[3:0];
endcase
end
endmodule // module_wrap64_setKind

129
module_wrap64_setOffset.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_setOffset O 116
// wrap64_setOffset_cap I 115
// wrap64_setOffset_offset I 32
//
// Combinational paths from inputs to outputs:
// (wrap64_setOffset_cap, wrap64_setOffset_offset) -> wrap64_setOffset
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_setOffset(wrap64_setOffset_cap,
wrap64_setOffset_offset,
wrap64_setOffset);
// value method wrap64_setOffset
input [114 : 0] wrap64_setOffset_cap;
input [31 : 0] wrap64_setOffset_offset;
output [115 : 0] wrap64_setOffset;
// signals for module outputs
wire [115 : 0] wrap64_setOffset;
// remaining internal signals
reg [1 : 0] mask__h560;
wire [31 : 0] addBase__h594, result_d_address__h572, x__h488;
wire [23 : 0] highOffsetBits__h80, mask__h595, signBits__h77, x__h107;
wire [9 : 0] x__h645;
wire [7 : 0] newAddrBits__h559,
result_d_addrBits__h573,
toBoundsM1__h90,
toBounds__h89;
wire [3 : 0] IF_wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wr_ETC___d62;
wire [2 : 0] repBound__h826;
wire IF_wrap64_setOffset_cap_BITS_31_TO_26_EQ_26_6__ETC___d52,
IF_wrap64_setOffset_offset_BIT_31_THEN_NOT_wra_ETC___d19,
wrap64_setOffset_cap_BITS_17_TO_15_6_ULT_wrap6_ETC___d50,
wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wrap6_ETC___d49;
// value method wrap64_setOffset
assign wrap64_setOffset =
{ highOffsetBits__h80 == 24'd0 &&
IF_wrap64_setOffset_offset_BIT_31_THEN_NOT_wra_ETC___d19 ||
wrap64_setOffset_cap[31:26] >= 6'd24,
(highOffsetBits__h80 == 24'd0 &&
IF_wrap64_setOffset_offset_BIT_31_THEN_NOT_wra_ETC___d19 ||
wrap64_setOffset_cap[31:26] >= 6'd24) &&
wrap64_setOffset_cap[114],
result_d_address__h572,
result_d_addrBits__h573,
wrap64_setOffset_cap[73:10],
repBound__h826,
wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wrap6_ETC___d49,
wrap64_setOffset_cap_BITS_17_TO_15_6_ULT_wrap6_ETC___d50,
IF_wrap64_setOffset_cap_BITS_31_TO_26_EQ_26_6__ETC___d52,
IF_wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wr_ETC___d62 } ;
// remaining internal signals
assign IF_wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wr_ETC___d62 =
{ (wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wrap6_ETC___d49 ==
IF_wrap64_setOffset_cap_BITS_31_TO_26_EQ_26_6__ETC___d52) ?
2'd0 :
((wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wrap6_ETC___d49 &&
!IF_wrap64_setOffset_cap_BITS_31_TO_26_EQ_26_6__ETC___d52) ?
2'd1 :
2'd3),
(wrap64_setOffset_cap_BITS_17_TO_15_6_ULT_wrap6_ETC___d50 ==
IF_wrap64_setOffset_cap_BITS_31_TO_26_EQ_26_6__ETC___d52) ?
2'd0 :
((wrap64_setOffset_cap_BITS_17_TO_15_6_ULT_wrap6_ETC___d50 &&
!IF_wrap64_setOffset_cap_BITS_31_TO_26_EQ_26_6__ETC___d52) ?
2'd1 :
2'd3) } ;
assign IF_wrap64_setOffset_cap_BITS_31_TO_26_EQ_26_6__ETC___d52 =
result_d_addrBits__h573[7:5] < repBound__h826 ;
assign IF_wrap64_setOffset_offset_BIT_31_THEN_NOT_wra_ETC___d19 =
wrap64_setOffset_offset[31] ?
x__h488[7:0] >= toBounds__h89 :
x__h488[7:0] <= toBoundsM1__h90 ;
assign addBase__h594 =
{ {22{x__h645[9]}}, x__h645 } << wrap64_setOffset_cap[31:26] ;
assign highOffsetBits__h80 = x__h107 & mask__h595 ;
assign mask__h595 = 24'd16777215 << wrap64_setOffset_cap[31:26] ;
assign newAddrBits__h559 = wrap64_setOffset_cap[17:10] + x__h488[7:0] ;
assign repBound__h826 = wrap64_setOffset_cap[17:15] - 3'b001 ;
assign result_d_addrBits__h573 = { mask__h560, 6'd63 } & newAddrBits__h559 ;
assign result_d_address__h572 =
{ wrap64_setOffset_cap[113:90] & mask__h595, 8'd0 } +
addBase__h594 +
wrap64_setOffset_offset ;
assign signBits__h77 = {24{wrap64_setOffset_offset[31]}} ;
assign toBoundsM1__h90 = { 3'b110, ~wrap64_setOffset_cap[14:10] } ;
assign toBounds__h89 = 8'd224 - { 3'b0, wrap64_setOffset_cap[14:10] } ;
assign wrap64_setOffset_cap_BITS_17_TO_15_6_ULT_wrap6_ETC___d50 =
wrap64_setOffset_cap[17:15] < repBound__h826 ;
assign wrap64_setOffset_cap_BITS_25_TO_23_8_ULT_wrap6_ETC___d49 =
wrap64_setOffset_cap[25:23] < repBound__h826 ;
assign x__h107 = wrap64_setOffset_offset[31:8] ^ signBits__h77 ;
assign x__h488 = wrap64_setOffset_offset >> wrap64_setOffset_cap[31:26] ;
assign x__h645 =
{ wrap64_setOffset_cap[1:0], wrap64_setOffset_cap[17:10] } ;
always@(wrap64_setOffset_cap)
begin
case (wrap64_setOffset_cap[31:26])
6'd25: mask__h560 = 2'b01;
6'd26: mask__h560 = 2'b0;
default: mask__h560 = 2'b11;
endcase
end
endmodule // module_wrap64_setOffset

48
module_wrap64_setPerms.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_setPerms O 115
// wrap64_setPerms_cap I 115
// wrap64_setPerms_perms I 31
//
// Combinational paths from inputs to outputs:
// (wrap64_setPerms_cap, wrap64_setPerms_perms) -> wrap64_setPerms
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_setPerms(wrap64_setPerms_cap,
wrap64_setPerms_perms,
wrap64_setPerms);
// value method wrap64_setPerms
input [114 : 0] wrap64_setPerms_cap;
input [30 : 0] wrap64_setPerms_perms;
output [114 : 0] wrap64_setPerms;
// signals for module outputs
wire [114 : 0] wrap64_setPerms;
// value method wrap64_setPerms
assign wrap64_setPerms =
{ wrap64_setPerms_cap[114:74],
wrap64_setPerms_perms[11:0],
wrap64_setPerms_cap[61:0] } ;
endmodule // module_wrap64_setPerms

45
module_wrap64_setSoftPerms.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_setSoftPerms O 115
// wrap64_setSoftPerms_cap I 115
// wrap64_setSoftPerms_softperms I 16 unused
//
// Combinational paths from inputs to outputs:
// wrap64_setSoftPerms_cap -> wrap64_setSoftPerms
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_setSoftPerms(wrap64_setSoftPerms_cap,
wrap64_setSoftPerms_softperms,
wrap64_setSoftPerms);
// value method wrap64_setSoftPerms
input [114 : 0] wrap64_setSoftPerms_cap;
input [15 : 0] wrap64_setSoftPerms_softperms;
output [114 : 0] wrap64_setSoftPerms;
// signals for module outputs
wire [114 : 0] wrap64_setSoftPerms;
// value method wrap64_setSoftPerms
assign wrap64_setSoftPerms = wrap64_setSoftPerms_cap ;
endmodule // module_wrap64_setSoftPerms

46
module_wrap64_setValidCap.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:25 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_setValidCap O 115
// wrap64_setValidCap_cap I 115
// wrap64_setValidCap_valid I 1
//
// Combinational paths from inputs to outputs:
// (wrap64_setValidCap_cap, wrap64_setValidCap_valid) -> wrap64_setValidCap
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_setValidCap(wrap64_setValidCap_cap,
wrap64_setValidCap_valid,
wrap64_setValidCap);
// value method wrap64_setValidCap
input [114 : 0] wrap64_setValidCap_cap;
input wrap64_setValidCap_valid;
output [114 : 0] wrap64_setValidCap;
// signals for module outputs
wire [114 : 0] wrap64_setValidCap;
// value method wrap64_setValidCap
assign wrap64_setValidCap =
{ wrap64_setValidCap_valid, wrap64_setValidCap_cap[113:0] } ;
endmodule // module_wrap64_setValidCap

66
module_wrap64_toMem.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:26 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_toMem O 89
// wrap64_toMem_cap I 115
//
// Combinational paths from inputs to outputs:
// wrap64_toMem_cap -> wrap64_toMem
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_toMem(wrap64_toMem_cap,
wrap64_toMem);
// value method wrap64_toMem
input [114 : 0] wrap64_toMem_cap;
output [88 : 0] wrap64_toMem;
// signals for module outputs
wire [88 : 0] wrap64_toMem;
// remaining internal signals
wire [87 : 0] x__h467;
wire [13 : 0] IF_wrap64_toMem_cap_BIT_32_THEN_wrap64_toMem_c_ETC___d15;
// value method wrap64_toMem
assign wrap64_toMem = { wrap64_toMem_cap[114], x__h467 } ;
// remaining internal signals
assign IF_wrap64_toMem_cap_BIT_32_THEN_wrap64_toMem_c_ETC___d15 =
wrap64_toMem_cap[32] ?
{ wrap64_toMem_cap[23:21],
wrap64_toMem_cap[31:29],
wrap64_toMem_cap[17:13],
wrap64_toMem_cap[28:26] } :
wrap64_toMem_cap[23:10] ;
assign x__h467 =
{ wrap64_toMem_cap[73:61],
~wrap64_toMem_cap[60:57],
24'hAAAAAA ^ 24'hAAAAAA,
~wrap64_toMem_cap[32],
IF_wrap64_toMem_cap_BIT_32_THEN_wrap64_toMem_c_ETC___d15[13:10],
~IF_wrap64_toMem_cap_BIT_32_THEN_wrap64_toMem_c_ETC___d15[9:8],
IF_wrap64_toMem_cap_BIT_32_THEN_wrap64_toMem_c_ETC___d15[7:2],
~IF_wrap64_toMem_cap_BIT_32_THEN_wrap64_toMem_c_ETC___d15[1],
IF_wrap64_toMem_cap_BIT_32_THEN_wrap64_toMem_c_ETC___d15[0],
wrap64_toMem_cap[113:82] } ;
endmodule // module_wrap64_toMem

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module_wrap64_validAsType.v Normal file
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//
// Generated by Bluespec Compiler, version 2025.01.1 (build 65e3a87)
//
// On Tue Feb 17 13:06:26 GMT 2026
//
//
// Ports:
// Name I/O size props
// wrap64_validAsType O 1
// wrap64_validAsType_dummy I 115 unused
// wrap64_validAsType_checkType I 32
//
// Combinational paths from inputs to outputs:
// wrap64_validAsType_checkType -> wrap64_validAsType
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module module_wrap64_validAsType(wrap64_validAsType_dummy,
wrap64_validAsType_checkType,
wrap64_validAsType);
// value method wrap64_validAsType
input [114 : 0] wrap64_validAsType_dummy;
input [31 : 0] wrap64_validAsType_checkType;
output wrap64_validAsType;
// signals for module outputs
wire wrap64_validAsType;
// value method wrap64_validAsType
assign wrap64_validAsType = wrap64_validAsType_checkType <= 32'd11 ;
endmodule // module_wrap64_validAsType